Intel
®
LXT970A Dual-Speed Fast
Ethernet Transceiver
Datasheet
The Intel
®
LXT970A Dual-Speed Fast Ethernet Transceiver (called hereafter the LXT970A
Transceiver) is an enhanced derivative of the Intel
®
LXT970 10/100 Mbps Fast Ethernet PHY
Transceiver that supports selectable driver strength capabilities and link-loss criteria. The
LXT970A Transceiver supports 100BASE-TX, 10BASE-T, and 100BASE-FX applications. It
provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access
Controllers (MAC)s and a pseudo-ECL interface for use with 100BASE-FX fiber networks.
The LXT970A Transceiver supports full-duplex operation at 10 and 100 Mbps. Its operating
condition is set using auto-negotiation, parallel detection or manual control. The encoder may be
bypassed for symbol mode applications.
The LXT970A Transceiver is fabricated with an advanced CMOS process and requires only a
single 5V power supply. The MII may be operated independently with either a 5V or a 3.3V
supply.
Applications
■
■
Combination 10BASE-T/100BASE-TX
Network Interface Cards (NICs)
10/100 Switches, 10/100 Printservers
■
100BASE-FX Network Interface Cards
(NICs)
Product Features
■
■
■
■
■
IEEE 802.3 Compliant:
— 10BASE-T and 100BASE-TX using a
single RJ-45 connection.
— Supports auto-negotiation and parallel
detection for legacy systems.
— MII interface with extended register
capability.
Robust baseline wander correction
performance.
100BASE-FX fiber optic capable.
Standard CSMA/CD or full-duplex
operation.
Configurable via MII serial port or external
control pins.
■
■
■
■
■
■
Configurable for DTE or switch
applications.
CMOS process with single 5Vsupply
operation
with provision for interface to 3.3V MII
bus.
Integrated LED drivers.
Integrated supply monitor and line
disconnect during low supply fault.
Available in:
— 64-pin TQFP:
FALXT970ATC Transceiver
JALXT970ATC Transceiver (RoHS-
Compliant)
— 64-pin PQFP:
SLXT970AQC Transceiver
EGLXT970AQC Transceiveer (RoHS-
Compliant)
Commercial temperature range (0 - 70
o
C
ambient).
Order Number: 249099-002
25-Nov-2005
.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
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in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by
estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
The Intel
®
LXT970A Dual-Speed Fast Ethernet Transceiver may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at
http://www.intel.com.
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2005, Intel Corporation. All Rights Reserved.
Datasheet
Intel
®
LXT970A Dual-Speed Fast Ethernet Transceiver
Contents
1.0
2.0
Pin Assignments and Signal Descriptions
....................................................10
Functional Description
........................................................................................... 18
2.1
2.2
Introduction.......................................................................................................... 18
Interfaces (Network Media/Protocol Support) ..................................................... 19
2.2.1 Twisted-Pair Interface ............................................................................ 19
2.2.2 Fiber Interface ........................................................................................ 19
2.2.3 MII Interface ........................................................................................... 20
2.2.3.1 Selectable Driver Levels............................................................ 20
2.2.3.2 MII Data Interface ...................................................................... 21
2.2.3.3 Repeater Mode.......................................................................... 24
2.2.3.4 MII Management Interface ........................................................ 24
2.2.4 Hardware Control Interface .................................................................... 26
Operating Requirements .....................................................................................27
2.3.1 Power Supply Requirements ..................................................................27
2.3.1.1 Optional MII Power Supply ........................................................ 27
2.3.2 Reference Clock Requirements ............................................................. 28
2.3.2.1 Master Clock Mode ................................................................... 28
2.3.2.2 Slave Clock Mode ..................................................................... 28
2.3.3 Bias Circuit Requirements ...................................................................... 29
Initialization.......................................................................................................... 29
2.4.1 Control Mode Selection .......................................................................... 29
2.4.1.1 MDIO Control Mode ..................................................................29
2.4.1.2 Manual Control Mode ................................................................ 29
2.4.2 Link Configuration .................................................................................. 29
2.4.2.1 Manual Configuration ................................................................ 30
2.4.2.2 Auto-Negotiation/Parallel Detection .......................................... 30
2.4.2.3 Controlling Auto-Negotiation ..................................................... 31
Monitoring Operational Status............................................................................. 31
2.5.1 Monitoring Status via MII Registers........................................................ 31
2.5.2 Monitoring Status via Indicator Pins ....................................................... 32
100BASE-X Operation ........................................................................................ 32
2.6.1 100BASE-X MII Operations.................................................................... 32
2.6.2 100BASE-X Network Operations ...........................................................33
10BASE-T Operation........................................................................................... 35
2.7.1 10BASE-T MII Operations...................................................................... 35
2.7.2 10BASE-T Network Operations.............................................................. 35
Protocol Sublayer Operations ............................................................................. 35
2.8.1 PCS Sublayer......................................................................................... 35
2.8.1.1 100X Preamble Handling .......................................................... 36
2.8.1.2 10T Preamble Handling............................................................. 36
2.8.1.3 Data Errors (100X Only) ............................................................ 36
2.8.1.4 Collision Indication .................................................................... 37
2.8.1.5 SQE (10T Only) .........................................................................38
2.8.1.6 Jabber (10T Only) ..................................................................... 38
2.8.2 PMA Layer.............................................................................................. 38
2.8.2.1 100TX Link Options ................................................................... 38
2.3
2.4
2.5
2.6
2.7
2.8
Datasheet
3
Intel
®
LXT970A Dual-Speed Fast Ethernet Transceiver
2.8.3
2.8.4
2.8.5
2.8.6
2.8.7
2.8.8
2.8.9
2.8.2.2 10T Link Test............................................................................. 38
2.8.2.3 Carrier Sense (CRS) ................................................................. 39
Twisted-Pair PMD Layer ........................................................................ 39
2.8.3.1 Scrambler/Descrambler (100TX Only) ...................................... 39
2.8.3.2 Baseline Wander Correction
(100TX Only)39
2.8.3.3 Polarity Correction..................................................................... 39
Fiber PMD Layer .................................................................................... 39
Additional Operating Features ............................................................... 40
Low-Voltage-Fault Detect....................................................................... 40
Power Down Mode ................................................................................. 40
Software Reset....................................................................................... 40
Hardware Reset ..................................................................................... 40
3.0
Application Information
......................................................................................... 41
3.1
3.2
3.3
Magnetics Information ......................................................................................... 41
Crystal Information .............................................................................................. 41
Design Recommendations .................................................................................. 42
3.3.1 General Design Guidelines .................................................................... 42
3.3.2 Power Supply Filtering ........................................................................... 42
3.3.3 Ground Noise ......................................................................................... 43
3.3.4 Power and Ground Plane Layout Considerations .................................. 43
3.3.5 Interfaces for Twisted-Pair /Fiber ........................................................... 43
3.3.5.1 Twisted-Pair .............................................................................. 43
3.3.5.2 Fiber .......................................................................................... 44
3.3.6 Interface for the MII ................................................................................ 44
3.3.6.1 Transmit Hold Time Adjustment ................................................ 44
3.3.6.2 MII Terminations........................................................................ 44
3.3.7 Typical Application ................................................................................. 45
3.3.7.1 Voltage Divider For MF Inputs................................................... 45
4.0
5.0
6.0
7.0
Test Specifications
.................................................................................................. 47
Register Definitions
................................................................................................ 63
Mechanical Specifications
................................................................................... 73
6.1
Top Label Markings............................................................................................. 75
Ordering Information
.............................................................................................. 77
4
Datasheet
Intel
®
LXT970A Dual-Speed Fast Ethernet Transceiver
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
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25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Block Diagram ....................................................................................................... 9
Pin Assignments .................................................................................................10
Network Interface Card (NIC) Application .......................................................... 18
MII Interface ....................................................................................................... 20
MII Data Interface ............................................................................................... 21
Loopback Paths .................................................................................................. 23
Repeater Block Diagram .................................................................................... 24
MDIO Interrupt Signaling .................................................................................... 25
Management Interface - Read Frame Structure ................................................. 25
Management Interface - Write Frame Structure ................................................. 26
Initialization Sequence ....................................................................................... 30
Auto-Negotiation Operation ................................................................................ 31
100BASE-TX Frame Structure ........................................................................... 33
100BASE-TX Data Flow .....................................................................................33
Protocol Sublayers ............................................................................................. 36
100BASE-TX Reception with No Errors ............................................................. 37
00BASE-TX Reception with Invalid Symbol ....................................................... 37
00BASE-TX Transmission with No Errors .......................................................... 37
00BASE-TX Transmission with Collision ............................................................ 37
Voltage Divider ................................................................................................... 45
Typical Interface Circuitry ................................................................................... 46
MII - 100BASE-TX Receive Timing / 4B Mode ................................................... 51
MII - 100BASE-TX Transmit Timing / 4B Mode ................................................. 52
MII - 100BASE-TX Receive Timing / 5B Mode ................................................... 53
100BASE-TX Transmit Timing / 5B Mode .......................................................... 54
MII - 100BASE-FX Receive Timing / 4B Mode ................................................... 55
MII - 100BASE-FX Transmit Timing / 4B Mode .................................................. 56
MII - 10BASE-T Receiving Timing ...................................................................... 57
MII - 10BASE-T Transmit Timing .......................................................................58
10BASE-T SQE (Heartbeat) Timing ................................................................... 59
10BASE-T Jab and Unjab Timing ...................................................................... 59
Auto Negotiation and Fast Link Pulse Timing ....................................................60
Fast Link Pulse Timing ....................................................................................... 60
MDIO Timing when Sourced by STA ................................................................. 61
MDIO Timing when Sourced by PHY ................................................................. 61
Power-Down Recovery Timing (Over Recommended Range) ........................... 62
PHY Identifier Bit Mapping ................................................................................. 66
64-Pin QFP Package Diagram ........................................................................... 73
64-Pin TQFP Package Diagram .........................................................................74
Sample TQFP Package – Intel
®
FALXT970ATC Transceiver............................. 75
Sample Pb-Free (RoHS-Compliant) TQFP Package – Intel
®
JALXT970ATC
Transceiver75
Sample PQFP Package – Intel
®
SLXT970AQC Transceiver .............................. 76
Sample Pb-Free (RoHS-Compliant) PQFP Package – Intel
®
EGLXT970AQC
Transceiver76
Ordering Information Matrix – Sample ................................................................ 78
Datasheet
5
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