MB95200H/210H Series
F
2
MC-8FX 8-bit Microcontroller
MB95200H/210H is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the
microcontrollers of this series contain a variety of peripheral resources.
Features
F
2
MC-8FX CPU core
Instruction set optimized for controllers
■
■
■
■
Low power consumption (standby) mode
■
■
■
■
Stop mode
Sleep mode
Watch mode
Timebase timer mode
Multiplication and division instructions
16-bit arithmetic operations
Bit test branch instructions
Bit manipulation instructions, etc.
I/O port (Max: 17) (MB95F204K/F203K/F202K)
■
Clock (main OSC clock and sub-OSC clock are only
available in MB95F204H/F204K/F203H/F203K/F202H
/F202K)
■
General-purpose I/O ports (Max):
CMOS I/O: 15, N-ch open drain: 2
Selectable main clock source
❐
Main OSC clock (up to 16.25 MHz, maximum machine clock
frequency: 8.125 MHz)
❐
External clock (up to 32.5 MHz, maximum machine clock
frequency: 16.25 MHz)
❐
Main internal CR clock (1/8/10 MHz ± 3%, maximum machine
clock frequency: 10 MHz)
Selectable subclock source
❐
Sub-OSC clock (32.768 kHz)
❐
External clock (32.768 kHz)
❐
Sub-internal CR clock (Typ: 100 kHz, Min: 50 kHz,
Max: 200 kHz)
I/O port (Max: 16) (MB95F204H/F203H/F202H)
■
General-purpose I/O ports (Max):
CMOS I/O: 15, N-ch open drain: 1
I/O port (Max: 5) (MB95F214K/F213K/F212K)
■
General-purpose I/O ports (Max):
CMOS I/O: 3, N-ch open drain: 2
■
I/O port (Max: 4) (MB95F214H/F213H/F212H)
■
General-purpose I/O ports (Max):
CMOS I/O: 3, N-ch open drain: 1
Timer
■
■
■
On-chip debug
■
■
8/16-bit composite timer
Timebase timer
Watch prescaler
1-wire serial control
Serial writing supported (asynchronous mode)
Hardware/software watchdog timer
■
LIN-UART (MB95F204H/F204K/F203H/F203K/F202H
/F202K)
■
Built-in hardware watchdog timer
Low-voltage detection reset circuit
■
Full duplex double buffer
❐
Capable of clock-synchronized serial data transfer and
clock-asynchronized serial data transfer
Built-in low-voltage detector
Clock supervisor counter
■
External interrupt
■
■
Built-in clock supervisor counter function
Interrupt by edge detection (rising edge, falling edge, and both
edges can be selected)
Can be used to wake up the device from different low-power
consumption (standby) modes
Programmable port input voltage level
■
CMOS input level / hysteresis input level
Flash memory security function
■
8/10-bit A/D converter
■
Protects the contents of flash memory
8-bit or 10-bit resolution can be selected.
Cypress Semiconductor Corporation
Document Number: 002-07463 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 18, 2016
MB95200H/210H Series
Contents
Product Line-up ................................................................ 3
Packages and Corresponding Products ........................ 4
Differences Among Products And Notes
On Product Selection ....................................................... 4
Pin Assignment ................................................................ 5
Pin Description (MB95200H Series 24 pins) .................. 6
Pin Description (MB95200H Series 20 pins) .................. 8
Pin Description (MB95210H Series) .............................. 10
I/O Circuit Type ............................................................... 11
Notes on Device Handling ............................................. 13
Pin Connection ............................................................... 13
Block Diagram (MB95200H Series) ............................... 15
Block Diagram (MB95210H Series) ............................... 16
CPU Core ......................................................................... 17
I/O Map (MB95200H Series) ........................................... 18
I/O Map (MB95210H Series) ........................................... 22
Interrupt Source Table (MB95200H Series) .................. 26
Interrupt Source Table (MB95210H Series) .................. 27
Electrical Characteristics ............................................... 28
Absolute Maximum Ratings ....................................... 28
Recommended Operating Conditions ....................... 30
DC Characteristics .................................................... 31
AC Characteristics ..................................................... 34
A/D Converter ............................................................ 49
Flash Memory Program/Erase Characteristics .......... 53
Sample Electrical Characteristics ................................. 54
Mask Options .................................................................. 60
Ordering Information ...................................................... 60
Package Dimensions ...................................................... 61
Major Changes ................................................................ 65
Document History ........................................................... 65
Document Number: 002-07463 Rev. *A
Page 2 of 66
MB95200H/210H Series
1. Product Line-up
Part number
Parameter
Type
MB95
F204H
MB95
F203H
MB95
F202H
MB95
F204K
MB95
F203K
MB95
F202K
MB95
F214H
MB95
F213H
MB95
F212H
MB95
F214K
MB95
F213K
MB95
F212K
Flash memory product
Clock supervisor It supervises the main clock oscillation.
counter
ROM capacity
RAM capacity
Low-voltage
detection reset
Reset input
Dedicated
16 KB
496 B
8 KB
496 B
No
4 KB
240 B
16 KB
496 B
8 KB
496 B
Yes
Software select
Dedicated
4 KB
240 B
16 KB
496 B
8 KB
496 B
No
4 KB
240 B
16 KB
496 B
8 KB
496 B
Yes
Software select
4 KB
240 B
CPU functions
Number of basic instructions
Instruction bit length
Instruction length
Data bit length
Minimum instruction execution time
Interrupt processing time
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8, and 16 bits
: 61.5 ns (with machine clock = 16.25 MHz)
: 0.6 µs (with machine clock = 16.25 MHz)
I/O ports (Max): 4
CMOS: 3, N-ch: 1
I/O ports (Max): 5
CMOS: 3, N-ch: 2
General-purpose I/O ports (Max): 16
I/O
CMOS: 15, N-ch: 1
Timebase timer
I/O ports (Max): 17
CMOS: 15, N-ch: 2
Interrupt cycle : 0.256 ms - 8.3 s (when external clock = 4 MHz)
Hardware/softwa Reset generation cycle
Main oscillation clock at 10 MHz : 105 ms (Min)
re watchdog
The sub-CR clock can be used as the source clock of the hardware watchdog.
timer
Wild register
It can be used to replace three bytes of data.
A wide range of communication speed can be selected
by a dedicated reload timer.
It has a full duplex double buffer.
Clock-synchronized serial data transfer and
No LIN-UART
clock-asynchronized serial data transfer is enabled.
The LIN function can be used as a LIN master or a LIN
slave.
6 ch.
8-bit or 10-bit resolution can be selected.
2 ch.
8/16-bit
composite timer
1 ch.
The timer can be configured as an "8-bit timer x 2 channels" or a "16-bit timer x 1 channel".
It has built-in timer function, PWC function, PWM function and input capture function.
Count clock: it can be selected from internal clocks (seven types) and external clocks.
It can output square wave.
6 ch.
2 ch.
2 ch.
LIN-UART
8/10-bit A/D
converter
External interrupt Interrupt by edge detection (rising edge, falling edge, or both edges can be selected.)
It can be used to wake up the device from standby modes.
On-chip debug
1-wire serial control
It supports serial writing. (asynchronous mode)
(Continued)
Document Number: 002-07463 Rev. *A
Page 3 of 66
MB95200H/210H Series
(Continued)
Part number
Parameter
Watch prescaler
MB95
F204H
MB95
F203H
MB95
F202H
MB95
F204K
MB95
F203K
MB95
F202K
MB95
F214H
MB95
F213H
MB95
F212H
MB95
F214K
MB95
F213K
MB95
F212K
Eight different time intervals can be selected.
It supports automatic programming, Embedded Algorithm,
write/erase/erase-suspend/erase-resume commands.
It has a flag indicating the completion of the operation of Embedded Algorithm.
Number of write/erase cycles: 100000
Data retention time: 20 years
For write/erase, external Vpp(+10 V) input is required.
Flash Security Feature for protecting the contents of the flash
Sleep mode, stop mode, watch mode, timebase timer mode
SDIP-24
SOP-20
DIP-8
SOP-8
Flash memory
Standby mode
Package
2. Packages and Corresponding Products
Part number
Package
24-pin plastic
SDIP
20-pin plastic
SOP
8-pin plastic DIP
8-pin plastic SOP
O: Available
X: Unavailable
MB95
F204H
O
O
X
X
MB95
F203H
O
O
X
X
MB95
F202H
O
O
X
X
MB95
F204K
O
O
X
X
MB95
F203K
O
O
X
X
MB95
F202K
O
O
X
X
MB95
F214H
X
X
O
O
MB95
F213H
X
X
O
O
MB95
F212H
X
X
O
O
MB95
F214K
X
X
O
O
MB95
F213K
X
X
O
O
MB95
F212K
X
X
O
O
3. Differences Among Products And Notes On Product Selection
Current consumption
When using the on-chip debug function, take account of the current consumption of flash erase/program.
For details of current consumption, see “18.Electrical Characteristics”.
Package
For details of information on each package, see “2.Packages and Corresponding Products” and “22.Package Dimensions”.
Operating voltage
The operating voltage varies, depending on whether the on-chip debug function is used or not.
For details of the operating voltage, see “18.Electrical Characteristics”.
On-chip debug function
The on-chip debug function requires that V
CC
, V
SS
and 1 serial-wire be connected to an evaluation tool. In addition, if the flash memory
data has to be updated, the RSTX/PF2 pin must also be connected to the same evaluation tool.
Document Number: 002-07463 Rev. *A
Page 4 of 66
MB95200H/210H Series
4. Pin Assignment
X0/PF0
N.C.
X1/PF1
Vss
X1A/PG2
X0A/PG1
Vcc
C
RSTX/PF2
TO10/P62
N.C.
TO11/P63
1
2
3
4
5
6
7
8
9
10
11
12
* The number of usable pins is 20.
24
23
P12/EC0/DBG
N.C.
P07/INT07
P06/INT06/TO01
P05/INT05/AN05/TO00/HCLK2
P04/INT04/AN04/SIN/HCLK1/EC0
P03/INT03/AN03/SOT
P02/INT02/AN02/SCK
P01/AN01
P00/AN00
N.C.
P64/EC1
(TOP VIEW)
24 pins
(SDIP24)
22
21
20
19
18
17
16
15
14
13
X0/PF0
X1/PF1
Vss
X1A/PG2
X0A/PG1
Vcc
C
RSTX/PF2
TO10/P62
TO11/P63
1
2
3
4
5
6
7
8
9
10
20
19
P12/EC0/DBG
P07/INT07
P06/INT06/TO01
P05/INT05/AN05/TO00/HCLK2
P04/INT04/AN04/SIN/HCLK1/EC0
P03/INT03/AN03/SOT
P02/INT02/AN02/SCK
P01/AN01
P00/AN00
P64/EC1
(TOP VIEW)
20 pins
18
17
16
15
14
13
12
11
Vss
Vcc
C
RSTX/PF2
1
2
3
4
(TOP VIEW)
8 pins
8
7
6
5
P12/EC0/DBG
P06/INT06/TO01
P05/AN05/TO00/HCLK2
P04/INT04/AN04/HCLK1/EC0
Document Number: 002-07463 Rev. *A
Page 5 of 66
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