Low Power CMOS Output VCXO Family (17MHz to 130MHz)
FEATURES
VCXO output for the 17MHz to 130MHz range
-
PLL500-17B: 17MHz to 36MHz
-
PLL500-27B: 27MHz to 65MHz
-
PLL500-37B: 65MHz to 130MHz
Low phase noise.
CMOS output with OE tri-state control.
Selectable output drive
-
Standard: 8mA drive capability.
-
High: 24mA drive capability.
Fundamental crystal input.
Integrated high linearity variable capacitors.
+/- 150 ppm pull range, max 5% linearity.
Low jitter (RMS): 2.5ps period jitter.
2.5V ~ 3.3V operation.
Available in 8-Pin SOP or Die.
PIN CONFIGURATION
XIN
OE^
VCON
GND
1
8
XOUT
DRIVSEL^
VDD
CLK
P500-x7B
2
3
4
7
6
5
^: Denotes internal Pull-up
DIE PAD LAYOUT
32 mil
(812,986)
8
1
XIN
XOUT
DRIVSEL^ 7
39 mil
2
OE^
VDD 6
DESCRIPTION
The PLL500-17B/27B/37B are a low cost, high per-
formance, low phase noise, and high linearity VCXO
family for the 17 to 130MHz range, providing less
than -130dBc/Hz at 10kHz offset. The very low jitter
(2.5 ps RMS period jitter) makes these chips ideal
for applications requiring voltage controlled fre-
quency sources. The IC’s are designed to accept
fundamental resonant mode crystals.
3 VCON
4 GND
CLK 5
DIE ID:
PLL500-17B: C500A-0505-05P
Y
X
PLL500-27B: C500A-0505-05Q
PLL500-37B: C500A-0505-05R
(0,0)
Note: ^ Denotes internal pull up
FREQUENCY RANGE
PART #
PLL500-17B
PLL500-27B
PLL500-37B
MULTIPLIER
No PLL
No PLL
No PLL
FREQUENCY
17 – 36 MHz
27 – 65 MHz
65 – 130 MHz
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
39 x 32 mil
GND
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
XIN
XOUT
XTAL
OSC
VARICAP
OE
CLK
VCON
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/30/07 Page 1
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
PIN AND PAD DESCRIPTION
Name
XIN
OE
VCON
GND
CLK
VDD
DRIVSEL
XOUT
Pin#
1
2
3
4
5
6
7
8
Die Pad Position
X (m)
94.183
94.157
94.183
94.193
715.472
715.307
715.472
476.906
Y (m)
768.599
605.029
331.756
140.379
203.866
455.726
626.716
888.881
Type
I
I
I
P
O
P
I
I
Crystal input pin.
Output Enable input pin. Disables the output when pulled
to “0”. Internal pull-up enables output by default if pin is
not connected.
Frequency control voltage input pin.
Ground pin.
Clock output pin.
VDD power supply pin.
Output drive select pin. High drive if set to ‘0’. Standard
drive if set to ‘1’. Internal pull-up.
Crystal output pin.
Description
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, DC
Output Voltage, DC
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
-0.5
-0.5
-65
-40
MIN.
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
C
C
C
C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/30/07 Page 2
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
2. AC Electrical Specifications
PARAMETERS
Input Crystal Frequency
T
R
/T
F
T
R
/T
F
SYMBOL
CONDITIONS
PLL500-17B
PLL500-27B
PLL500-47B
Output Clock Rise/Fall Time
Output Clock Duty Cycle
Short Circuit Current
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
Power Supply Rejection
VCON pin input impedance
VCON modulation BW
0V < VCON < 3.3V, -3dB
-17B
-27B
-37B
PWSRR
Frequency change with
VDD varied +/- 10%
-1
2000
18
18
25
MIN.
17
27
65
TYP.
MAX.
36
65
130
UNITS
MHz
0.8V ~ 2.0V with 10 pF load
0.3V ~ 3.0V with 15 pF load
Measured @ 1.4V (3.3V)
45
0.8
2.5
50
50
55
ns
%
mA
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
XTAL C
0
/C
1
< 250
0V
VCON
3.3V
VCON=1.65V,
1.65V
MIN.
TYP.
MAX.
10
UNITS
ms
ppm
ppm
300
150
100
5
+1
ppm/V
%
ppm
k
kHz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/30/07 Page 3
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
4. Jitter and Phase Noise Specifications
PARAMETERS
RMS Period Jitter
(1 sigma – 10,000 samples)
CONDITIONS
With capacitive decoupling
between VDD and GND.
MIN
TYP
2.5
MAX
UNITS
ps
PLL500-17B
Phase Noise relative to carrier at 27MHz
Phase Noise relative to carrier at 27MHz
Phase Noise relative to carrier at 27MHz
Phase Noise relative to carrier at 27MHz
PLL500-27B
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Noise
Noise
Noise
Noise
Noise
Noise
Noise
Noise
Noise
relative
relative
relative
relative
relative
relative
relative
relative
relative
to
to
to
to
to
to
to
to
to
carrier
carrier
carrier
carrier
carrier
carrier
carrier
carrier
carrier
at
at
at
at
at
at
at
at
at
61.44MHz
61.44MHz
61.44MHz
61.44MHz
77.76MHz
77.76MHz
77.76MHz
77.76MHz
77.76MHz
@100Hz offset
@1kHz offset
@10kHz offset
@100kHz offset, and 1MHz
@100Hz offset
@1kHz offset
@10kHz offset
@100kHz offset
@1MHz offset
-100
-125
-142
-150
-100
-125
-142
-150
-152
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@100Hz offset
@1kHz offset
@10kHz offset
@100kHz offset, and 1MHz
-100
-125
-142
-150
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
PLL500-37B
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/30/07 Page 4
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
5. DC Specifications
PARAMETERS
SYMBOL
CONDITIONS
27MHz, 15pF output load, 3.3V
35MHz, 15pF output load, 3.3V
Supply Current,
Dynamic, with
Loaded Outputs
I
DD
78MHz, 15pF output load, 3.3V
27MHz, 15pF output load, 2.5V
35MHz, 15pF output load, 2.5V
78MHz, 15pF output load, 2.5V
PLL500-17B
Allowable output load
capacitance
C
L
(Output)
PLL500-27B
PLL500-37B Std drive <100MHz
PLL500-37B High drive
Operating Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
at CMOS level
Output drive current
Short Circuit Current
VCXO Control Voltage
VCON
0
V
DD
V
OH
V
OL
I
OH
= -8mA, 3.3V Supplies
I
OL
= 8mA, 3.3V Supplies
I
OH
= -4mA, 3.3V Supplies
Standard drive, 3.3V
High drive, 3.3V
V
DD
– 0.4
8
24
9.5
27
50
V
DD
2.25
2.4
0.4
MIN.
TYP.
3.7
4.2
7.2
2.4
2.8
5.2
MAX.
5
6
9
3.5
4
7
30
20
15
10
3.63
pF
pF
pF
pF
V
V
V
V
mA
mA
V
mA
UNITS
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/30/07 Page 5
微控制器 MCU
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