IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER W/PARITY CHECKER
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 12-BIT UNIVERSAL
BUS DRIVER WITH PARITY
CHECKER, DUAL 3-STATE
OUTPUTS AND BUS-HOLD
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
– Extended commercial range of – 40°C to + 85°C
– V
CC
= 3.3V ± 0.3V, Normal Range
– V
CC
= 2.7V to 3.6V, Extended Range
– V
CC
= 2.5V ± 0.2V
– CMOS power levels (0.4µ W typ. static)
– Rail-to-Rail output swing for increased noise margin
Drive Features for ALVCH16903:
– High Output Drivers: ±24mA
– Suitable for heavy loads
–
–
–
IDT74ALVCH16903
DESCRIPTION:
This 12-bit universal bus driver is built using advanced dual metal
CMOS technology. This device has dual outputs and can operate as a
buffer or an edge-triggered register. In both modes, parity is checked on
APAR, which arrives one cycle after the data to which it applies. The
YERR output, which is produced one cycle after APAR, is open drain.
MODE selects one of the two data paths. When MODE is low, the
device operates as an edge-triggered register. On the positive transition
of the clock (CLK) input and when the clock-enable (CLKEN) input is low,
data setup at the A inputs is stored in the internal registers. On the positive
transition of CLK and when CLKEN is high, only data setup at the 9A-12A
inputs is stored in their internal registers. When MODE is high, the device
operates as a buffer and data at the A inputs passes directly to the
outputs. The 11A/YERREN serves a dual purpose; it acts as a normal
data bit and also enables YERR data to be clocked into the YERR output
register.
When used as a single device, parity output enable (PAROE) must be
tied high; when parity input/output (PARI/O) is low, even parity is selected
and when PARI/O is high, odd parity is selected. When used in pairs and
PAROE is low, the parity sum is output on PARI/O for cascading to the
second ALVCH16903. When used in pairs and PAROE is high, PARI/O
accepts a partial parity sum from the first ALVCH16903.
(1)
Unit
V
V
°C
mA
mA
mA
mA
NEW16link
APPLICATIONS:
•
3.3V High Speed Systems
•
3.3V and lower voltage computing systems
ABSOLUTE MAXIMUM RATING
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage
with Respect to GND
Terminal Voltage
with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
>
V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through
each V
CC
or GND
Max.
– 0.5 to + 4.6
– 0.5 to
V
CC
+ 0.5
– 65 to + 150
– 50 to + 50
± 50
– 50
±100
A buffered output-enable (OE) input can be used to place the 24
outputs and YERR in either a normal logic state (high or low logic levels)
or a high-impedance state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly. The high-impedance
state and increased drive provide the capability to drive bus lines without
need for interface or pullup components.
The ALVCH16903 has been designed with a ±24mA output driver.
This driver is capable of driving a moderate to heavy load while
maintaining speed performance.
The ALVCH16903 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high-impedance. This prevents
floating inputs and eliminates the need for pull-up/down resistors.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
APRIL 1999
DSC-4911/-
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER W/PARITY CHECKER
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40° C to +85° C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OH
I
OZ
(2)
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Ci
Co
Cio
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
Quiescent Power Supply
Current Variation
Control Inputs
Data Inputs
YERR Output
Data Outputs
PARI/O
V
CC
= 3.3V
V
O
= V
CC
or GND
V
CC
= 3.3V
V
O
= V
CC
or GND
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
YERR Output
V
CC
= 0V to 3.6V
V
CC
= 3.6V
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
−
0.6V,
other inputs at V
CC
or GND
V
CC
= 3.3V
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
V
O
= V
CC
V
O
= V
CC
or GND
Min.
1.7
2
—
—
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
—
—
– 0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
± 10
± 10
± 10
± 10
– 1.2
—
40
µA
µA
µA
µA
V
mV
µA
µA
V
Unit
V
—
V
I
= V
CC
or GND
—
—
—
—
—
—
5.5
5.5
5
6
7
750
—
—
—
—
—
µA
pF
pF
pF
NOTES:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
2. For I/O ports, the parameter Ioz includes the input leakage current.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
NEW16link
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3.0V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2.0V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
– 45
45
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
± 500
Unit
µA
µA
µA
4
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
