IA64F3048SEC
Security-Enhanced Microcontroller
Data Sheet
Copyright
©
2005
innovASIC
®
IA64F3048SEC
Security-Enhanced Microcontroller
Data Sheet
Version -01
Table of Contents
Please Note.....................................................................................................................................................3
Overview ........................................................................................................................................................3
Features ......................................................................................................................................................3
Compatibility .............................................................................................................................................4
Software Development Tools.....................................................................................................................4
Added Features ..........................................................................................................................................4
Functional Blocks ......................................................................................................................................4
Central Processing Unit (CPU) ......................................................................................................................6
MCU Operating Mode ...................................................................................................................................8
Internal Flash..................................................................................................................................................8
128K Embedded Flash Memory A and 1K Security Bits Features ...........................................................9
Internal RAM ...............................................................................................................................................10
32 x 32 Multiply Bit.....................................................................................................................................10
Hardware Random Number Generator ........................................................................................................11
Features ....................................................................................................................................................11
Input/Output Ports........................................................................................................................................12
Interrupt Controller ......................................................................................................................................13
Exception Sources....................................................................................................................................13
Bus Controller ..............................................................................................................................................13
Features ....................................................................................................................................................13
Refresh Controller........................................................................................................................................14
Direct Access Memory Controller (DMAC)................................................................................................14
Serial Communication Interface (SCI).........................................................................................................14
Smart Card Interface ....................................................................................................................................15
Analog to Digital Converter (ADC).............................................................................................................16
Digital to Analog Converter (DAC).............................................................................................................16
DAC Pin Descriptions..............................................................................................................................16
Integrated Timer Unit (ITU) ........................................................................................................................17
Programmable Timing Pattern Controller....................................................................................................17
Watchdog Timer (WDT)..............................................................................................................................17
Pinout ...........................................................................................................................................................18
Table of Figures
Figure 1. Block Diagram................................................................................................................................5
Figure 2. Memory Map ..................................................................................................................................7
Figure 3. 128K Flash Memory A and 1-Kbyte Security Bits Map ................................................................9
Figure 4. Pinout............................................................................................................................................18
Table 1. MLTXS.L Operand Format, Required States for Execution .........................................................11
Table 2. MLTXU.L Operand Format, Required States for Execution.........................................................11
Table 3. Operating Mode .............................................................................................................................20
Copyright
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2005
ENG21 1 040405-01
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The End of Obsolescence®
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IA64F3048SEC
Security-Enhanced Microcontroller
Data Sheet
Version -01
Please Note
This data sheet is designed to provide only a high-level overview of the IA64F3048SEC Security-
Enhanced Microcontroller. For a more detailed and comprehensive discussion of the IA64F3048SEC,
please refer to the
IA64F3048SEC Security-Enhanced Microcontroller Operator User’s Guide.
Overview
The IA64F3048SEC Security-Enhanced Microcontroller is the ideal solution for many embedded
applications, combining the flexibility of the H8300H family of microcontrollers with the power of its
additional on-chip features. This combination allows the development of more complex embedded
applications than are possible with the H8 alone. It also eases the implementation of the more robust
security features that are required of products today.
Features
Following are features of the IA64F3048SEC Security-Enhanced Microcontroller:
•
Hardware random number generator
•
Fast 32 x 32 hardware multiplier
•
Secure memory operation
•
8-kbytes SRAM (4 kbytes)
•
1 kbyte of flash security bits
•
32 kbytes of internal data flash memory
•
128 kbytes of internal program flash memory
•
Operation at up to 50 MHz
•
Sixteen 16-bit general registers
•
Flexible instruction set built on 62 basic instruction types
•
8/16/32-bit data transfer, arithmetic and logic instructions
•
Signed and unsigned multiply and divide instructions
•
Extensive bit manipulation instructions
•
Bus controller with 8- and 16-bit access
•
3-function refresh controller
•
DMA controller with short or full address mode
•
16-bit integrated timer unit (ITU) with 5 channels
•
Programmable timing pattern controller (TPC)
•
Watchdog timer
•
Serial communications interface (SCI) with built-in smart card interface
•
Eight 10-bit A/D converter channels
•
Two 8-bit D/A converter channels
•
Clock pulse generator
•
Interrupt controller with 37 sources
•
Seventy input/output pins and eight input-only pins
•
3.3V operation
•
Available in 100 pin QFP and TQFP packages
Copyright
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2005
ENG21 1 040405-01
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The End of Obsolescence®
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IA64F3048SEC
Security-Enhanced Microcontroller
Compatibility
Data Sheet
Version -01
The IA64F3048SEC provides an upward compatibility path for H8300H users who need higher
performance and on-chip security features. The IA64F3048SEC is code compatible with the H8300H
family of microcontrollers and is completely pin compatible with the 3.3V H83048F-ONE
microcontroller. The device is available in both QFP and TQFP packages.
Software Development Tools
The IA64F3048SEC software development tools are based on the popular GNU toolset of GCC. These
tools support the development of C and H8300 assembly language programs. Developers can compile,
assemble and link C and H8300 assembly language files to produce binary absolute files. These binary
absolute files can then be downloaded or programmed into the IA64F3048SEC development board for
debug and testing.
The development board software tools support-debugging applications are downloaded into RAM with
INSIGHT and the GNU GDB debugger. GDB stubs that execute in the target as a monitor program are
provided for debugging both RAM-based and ROM-based applications.
The development board software tools include a utility for programming both the internal Flash memory
of the IA64F3048SEC part and the external EEPROM located on the development board.
These tools can operate in either a LINUX environment or a Windows NT (Windows 2000, Windows XP
PRO) environment that has the CYGWIN toolset installed.
Added Features
The IA64F3048SEC offers all of the standard features of the advanced H83048 microcontroller series,
with an operating frequency of 50 MHz. In addition, InnovASIC has added new security-related features
that make the IA64F3048SEC a compelling choice for embedded applications requiring higher levels of
integrity, authenticity and data protection without loss of performance. These security features include an
extremely flexible 128 kbytes of non-volatile memory in two independent partitions. This non-volatile
memory has read-out protection and locking mechanisms to protect vital data. Additional security
enhancements include a high-quality physical random number generator.
Functional Blocks
The IA64F3048SEC microcontroller consists of the following functional blocks:
•
Central Processing Unit (CPU)
•
Memory Control Unit (MPU)
•
Interrupt Controller
•
Bus Controller
•
Refresh Controller
•
Direct Memory Access (DMA) Controller
•
Input/Output Ports
•
Integrated Timer Unit (ITU)
•
Programmable Timing Pattern Generator
•
Watchdog Timer
•
Serial Communication Interface
•
Smart Card Interface
Copyright
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2005
ENG21 1 040405-01
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The End of Obsolescence®
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IA64F3048SEC
Security-Enhanced Microcontroller
Data Sheet
Version -01
•
Analog to Digital Converter (ADC)
•
Digital to Analog Converter (DAC)
•
On-Chip RAM
•
On-Chip 128-kbyte Program Flash Memory
•
Clock Generator
•
32-kbyte Data Flash memory
•
32 x 32 hardware multiplier with a 64-bit result
•
Hardware Random Number Generator
A functional block diagram of the IA64F3048SEC is depicted in
Figure 1. Block Diagram.
Interrupt Controller
Refresh Controller
DMA Controller
Clock Generator (50 MHz)
128-kbyte Program
Flash
H8/300H
Compatible
CPU
with 32-Bit Multiplier
Memory Control Unit
Watchdog Timer
16-Bit ITU
Programmable
Timing Pattern
Generator (TPC)
SCI (2ch) with
SmartCard Interface
A/D Converter (8ch)
D/A Converter (2ch)
Random Number
Generator
32-kbyte Data
Flash
8-kbyte
SRAM
Bus Controller
PORT 6
PORT 5
PORT 4
PORT 3
PORT 2
PORT 1
PORT B
PORT A
PORT 9
PORT 8
PORT 7
innov
ASIC
IA64F3048SEC
Figure 1. Block Diagram
Copyright
©
2005
ENG21 1 040405-01
innovASIC
The End of Obsolescence®
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Customer Support:
1.888.824.4184
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