19-3802; Rev 2; 8/06
16-Channel Buffered CMOS
Logic-Level Translators
General Description
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-bit bidirectional CMOS logic-level translators pro-
vide the level shifting necessary to allow data transfer in
multivoltage systems. These devices are inherently
bidirectional due to their design and do not require the
use of a direction input. Externally applied voltages,
V
CC
and V
L
, set the logic levels on either side of the
devices. Logic signals present on the V
L
side of the
device appear as a higher voltage logic signal on the
V
CC
side of the device, and vice-versa.
The MAX13101E/MAX13102E/MAX13103E feature an
enable input (EN) that, when low, reduces the V
CC
and
V
L
supply currents to less than 2µA. The MAX13108E
features a multiplexing input (MULT) that selects one
byte between the two, thus allowing multiplexing of the
signals. The MAX13101E/MAX13102E/MAX13103E/
MAX13108E have ±15kV ESD protection on the I/O V
CC
side for greater protection in applications that route sig-
nals externally. Three different output configurations are
available during shutdown, allowing the I/O on the V
CC
side or the V
L
side to be put in a high-impedance state
or pulled to ground through an internal 6kΩ resistor.
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
accept V
CC
voltages from +1.65V to +5.5V and V
L
voltages from +1.2V to V
CC
, making them ideal for data
transfer between low-voltage ASICs/PLDs and higher
voltage systems. The MAX13101E/MAX13102E/
MAX13103E/MAX13108E are available in 36-bump
UCSP™ and 40-pin TQFN packages, and operate over
the extended -40°C to +85°C temperature range.
♦
Wide Supply Voltage Range
V
CC
Range of 1.65V to 5.5V
V
L
Range of 1.2V to V
CC
♦
ESD Protection on I/O V
CC
Lines
±15kV Human Body Model
♦
Up to 20Mbps Throughput
♦
Low 0.03µA Typical Quiescent Current
♦
UCSP and TQFN Packages
Features
MAX13101E/MAX13102E/MAX13103E/MAX13108E
Pin Configurations
TOP VIEW OF BOTTOM LEADS
I/O V
CC
10
I/O V
CC
11
I/O V
CC
5
I/O V
CC
6
I/O V
CC
7
I/O V
CC
8
I/O V
CC
9
GND
I/O V
CC
12
22
GND
21
20 I/O V
CC
13
19 I/O V
CC
14
18 I/O V
CC
15
17 I/O V
CC
16
16 V
CC
15 V
L
14 I/O V
L
16
*EP
13 I/O V
L
15
12 I/O V
L
14
11 I/O V
L
13
1
GND
2
I/O V
L
5
3
I/O V
L
6
4
I/O V
L
7
5
I/O V
L
8
6
I/O V
L
9
7
I/O V
L
10
8
I/O V
L
11
9
I/O V
L
12
10
EN
30
I/O V
CC
4
I/O V
CC
3
I/O V
CC
2
I/O V
CC
1
V
CC
V
L
I/O V
L
1
I/O V
L
2
I/O V
L
3
I/O V
L
4
31
32
33
34
35
36
37
38
39
40
29
28
27
26
25
24
23
MAX13101E
MAX13102E
MAX13103E
Applications
CMOS Logic-Level
Translation
Portable Equipment
Cell Phones
PDAs
Digital Still Cameras
Smart Phones
*EXPOSED PADDLE CONNECTED TO GROUND
TQFN
Pin Configurations continued at end of data sheet.
Typical Operating Circuit appears at end of data sheet.
Ordering Information/Selector Guide
PART
PIN-PACKAGE
36 UCSP**
3.06mm x 3.06mm
40 TQFN
5mm x 5mm x 0.8mm
DATA
RATE
(Mbps)
20
20
I/O V
L
STATE
DURING SHUTDOWN
High impedance
High impedance
I/O V
CC
STATE
DURING SHUTDOWN
6kΩ to GND
6kΩ to GND
MULTIPLEXER
FEATURE
No
No
PKG
CODE
B36-1
T4055-1
MAX13101EEBX*
MAX13101EETL
Note:
All devices operate over the -40°C to +85°C operating temperature range.
*Future
product—contact factory for availability.
**UCSP bumps are in a 6 x 6 array.
Ordering Information/Selector Guide continued at end of data sheet.
UCSP is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
16-Channel Buffered CMOS
Logic-Level Translators
MAX13101E/MAX13102E/MAX13103E/MAX13108E
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.)
V
CC
...........................................................................-0.3V to +6V
V
L...........................................................................................
-0.3V to +6V
I/O V
CC_
......................................................-0.3V to (V
CC
+ 0.3V)
I/O V
L_ .....................................................................
-0.3V to (V
L
+ 0.3V)
EN, MULT .................................................................-0.3V to +6V
Short-Circuit Duration I/O V
L_
, I/O V
CC_
to GND .......Continuous
Continuous Power Dissipation (T
A
= +70°C)
36-Bump UCSP (derate 17.0mW/°C above +70°C) ..1361mW
40-Pin TQFN (derate 35.7mW/°C above +70°C) .......2857mW
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +1.65V to +5.5V, V
L
= +1.2V to V
CC
, EN = V
L
(MAX13101E/MAX13102E/MAX13103E), MULT = V
L
or GND (MAX13108E),
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V
CC
= +1.65V, V
L
= +1.2V, T
A
= +25°C.)
(Notes 1, 2)
PARAMETER
POWER SUPPLIES
V
L
Supply Range
V
CC
Supply Range
Supply Current from V
CC
V
L
V
CC
I
QVCC
I/O V
CC
_ = GND, I/O V
L
_ = GND
or I/O V
CC
_ = V
CC
, I/O V
L
_ = V
L
,
EN = V
L
, MULT = GND or V
L
I/O V
CC
_ = GND, I/O V
L
_ = GND
or I/O V
CC
_ = V
CC
, I/O V
L
_ = V
L
,
EN = V
L
, MULT = GND or V
L
T
A
= +25°C, EN = GND, I/O V
CC
_ = GND,
I/O V
L
_ = GND,
MAX13101E/MAX13102E/MAX13103E
T
A
= +25°C, EN = GND, I/O V
CC
_ = GND,
I/O V
L
_ = GND,
MAX13101E/MAX13102E/MAX13103E
T
A
= +25°C, EN = GND,
MAX13102E/MAX13103E
I/O V
CC
_ Tri-State Output
Leakage Current
T
A
= +25°C, MULT = GND (I/O V
CC
1 - I/O V
CC
8)
or MULT = V
L
(I/O V
CC
9 - I/O V
CC
16)
MAX13108E
T
A
= +25°C, EN = GND, MAX13101E/
MAX13103E
I/O V
L
_ Tri-State Output Leakage
Current
T
A
= +25°C, MULT = GND (I/O V
L
1 - I/O
V
L
8) or MULT = V
L
(I/OV
L
9 - I/O V
L
16)
MAX13108E
EN = GND, MAX13102E
4
1.2
1.65
0.03
V
CC
5.50
10
V
V
µA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current from V
L
I
QVL
0.03
20
µA
V
CC
Shutdown Supply Current
I
SHDN-VCC
0.03
1
µA
V
L
Shutdown Supply Current
I
SHDN-VL
0.03
2
µA
0.02
1
µA
0.02
1
0.02
1
µA
0.02
1
I/O V
L
_ Pulldown Resistance
During Shutdown
10
kΩ
2
_______________________________________________________________________________________
16-Channel Buffered CMOS
Logic-Level Translators
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +1.65V to +5.5V, V
L
= +1.2V to V
CC
, EN = V
L
(MAX13101E/MAX13102E/MAX13103E), MULT = V
L
or GND (MAX13108E),
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V
CC
= +1.65V, V
L
= +1.2V, T
A
= +25°C.) (Notes 1, 2)
PARAMETER
I/O V
CC
_ Pulldown Resistance
During Shutdown
EN or MULT Input Leakage
Current
LOGIC-LEVEL THRESHOLDS
I/O V
L
_ Input-Voltage High
Threshold
I/O V
L
_ Input-Voltage Low
Threshold
I/O V
CC
_ Input-Voltage High
Threshold
I/O V
CC
_ Input-Voltage Low
Threshold
EN, MULT Input-Voltage High
Threshold
EN, MULT Input-Voltage Low
Threshold
I/O V
L
_ Output-Voltage High
I/O V
L
_ Output-Voltage Low
I/O V
CC
_ Output-Voltage High
I/O V
CC
_ Output-Voltage Low
V
IHL
V
ILL
V
IHC
V
ILC
V
IH-SHDN
V
IL-SHDN
V
OHL
V
OLL
V
OHC
V
OLC
0.4
I/O V
L
_ source current = 20µA, I/O V
CC
_
≥
V
IHC
V
L
- 0.4
I/O V
L
_ sink current = 20µA, I/O V
CC
_
≤
V
ILC
I/O V
CC
_ source current = 20µA, I/O V
L
_
≥
V
IHL
V
CC
- 0.4
I/O V
CC
_ sink current = 20µA, I/O V
L
_
≤
V
ILL
I/O V
CC
side
I/O V
L
side
V
L
= 1.2V, V
CC
= 1.65V
V
L
= 1.2V, V
CC
= 1.65V
V
L
= 5V, V
CC
= 5V
V
L
= 1.2V, V
CC
= 1.65V
V
L
= 5V, V
CC
= 5V
V
L
= 1.2V, V
CC
= 1.65V
V
L
= 5V, V
CC
= 5V
V
L
= 1.2V, V
CC
= 1.65V
V
L
= 5V, V
CC
= 5V
Human Body Model
V
CC
/ 2
V
L
/ 2
20
60
5
15
5
30
5
20
7
±15
0.4
0.4
1/3 x
V
CC
V
L
- 0.4
1/3 x
V
L
2/3 x
V
CC
2/3 x
V
L
V
V
V
V
V
V
V
V
V
V
SYMBOL
CONDITIONS
EN = GND, MAX13101E
T
A
= +25°C
MIN
4
TYP
MAX
10
1
UNITS
kΩ
µA
MAX13101E/MAX13102E/MAX13103E/MAX13108E
RISE/FALL-TIME ACCELERATOR STAGE
Transition-Detect Threshold
Accelerator Pulse Duration
I/O V
L
_ Output-Accelerator Sink
Impedance
I/O V
CC
_ Output-Accelerator Sink
Impedance
I/O V
L
_ Output-Accelerator
Source Impedance
I/O V
CC
_ Output-Accelerator
Source Impedance
ESD PROTECTION
I/O V
CC
_
kV
V
ns
Ω
Ω
Ω
Ω
_______________________________________________________________________________________
3
16-Channel Buffered CMOS
Logic-Level Translators
MAX13101E/MAX13102E/MAX13103E/MAX13108E
TIMING CHARACTERISTICS
(V
CC
= +1.65V to +5.5V, V
L
= +1.2V to V
CC
, EN = V
L
(MAX13101E/MAX13102E/MAX13103E), MULT = V
L
or GND (MAX13108E),
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V
CC
= +1.65V, V
L
= +1.2V, T
A
= +25°C.) (Notes 1, 2)
PARAMETER
I/O V
L
_ Rise Time
I/O V
L
_ Fall Time
I/O V
CC
_ Rise Time
I/O V
CC
_ Fall Time
Propagation Delay
(Driving I/O V
L
_)
Propagation Delay
(Driving I/O V
CC
_)
Channel-to-Channel Skew
Part-to-Part Skew
Propagation Delay from
I/O V
L
_ to I/O V
CC
_ After EN
Propagation Delay from
I/O V
CC
_ to I/O V
L
_ After EN
Maximum Data Rate
SYMBOL
t
RVL
t
FVL
t
RVCC
t
FVCC
t
PVL-VCC
t
PVCC-VL
t
SKEW
t
PPSKEW
t
EN-VCC
t
EN-VL
CONDITIONS
R
S
= 50Ω, C
I/OVL_
= 15pF, t
RISE
≤
3ns,
(Figures 2a, 2b)
R
S
= 50Ω, C
I/OVL_
= 15pF, t
FALL
≤
3ns,
(Figures 2a, 2b)
R
S
= 50Ω, C
I/OVCC_
= 50pF, t
RISE
≤
3ns,
(Figures 1a, 1b)
R
S
= 50Ω, C
I/OVCC_
= 50pF, t
FALL
≤
3ns,
(Figures 1a, 1b)
R
S
= 50Ω, C
I/OVCC_
= 50pF, t
RISE
≤
3ns,
(Figures 1a, 1b)
R
S
= 50Ω, C
I/OVL_
= 15pF, t
RISE
≤
3ns,
(Figures 2a, 2b)
R
S
= 50Ω, C
I/OVCC_
= 50pF, C
I/OVL_
=
15pF, t
RISE
≤
3ns
R
S
= 50Ω, C
I/OVCC_
= 50pF, C
I/OVL_
=
15pF, t
RISE
≤
3ns,
∆T
A
= +20°C (Notes 3, 4)
C
I/OVCC_
= 50pF (Figure 3)
C
I/OVL_
= 15pF (Figure 4)
R
SOURCE
= 50Ω, C
I/OVCC_
= 50pF,
C
I/OVL_
= 15pF, t
RISE
≤
3ns
20
MIN
TYP
MAX
15
15
15
15
20
20
5
10
1
1
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
Mbps
Note 1:
All units are 100% production tested at T
A
= +25°C. Limits over the operating temperature range are guaranteed by design
and not production tested.
Note 2:
For normal operation, ensure that V
L
< (V
CC
+ 0.3V). During power-up, V
L
> (V
CC
+ 0.3V) does not damage the device.
Note 3:
V
CC
from device 1 must equal V
CC
of device 2. V
L
from device 1 must equal V
L
of device 2.
Note 4:
Guaranteed by design, not production tested.
4
_______________________________________________________________________________________
16-Channel Buffered CMOS
Logic-Level Translators
Test Circuits/Timing Diagrams
t
RISE/FALL
≤
3ns
MAX13101E/MAX13102E/MAX13103E/MAX13108E
V
L
MAX13101E
MAX13102E
MAX13103E
MAX13108E
EN/(MULT)
6kΩ
I/O V
L_
6kΩ
I/O V
CC_
I/O V
L_
V
CC
90%
50%
10%
t
PLH
t
PHL
I/O V
CC_
50%
SOURCE
R
S
C
I/OVCC_
90%
50%
10%
90%
10%
ALL UNUSED I/O V
CC_
AND I/O V
L_
CONNECTED TO GND
( ) ARE FOR THE MAX13108E
t
PVL-VCC
= t
PHL
or t
PLH
t
FVCC
t
RVCC
Figure 1a. Driving I/O V
L_
Figure 1b. Timing for Driving I/O V
L_
t
RISE/FALL
≤
3ns
V
L
EN/(MULT)
MAX13101E
MAX13102E
MAX13103E
MAX13108E
6kΩ
R
S
I/O V
L_
C
I/OVL_
6kΩ
I/O V
CC_
V
CC
I/O V
CC_
90%
50%
10%
t
PLH
t
PHL
SOURCE
I/O V
L_
90%
50%
10%
10%
50%
90%
ALL UNUSED I/O V
CC_
AND I/O V
L_
CONNECTED TO GND
( ) ARE FOR THE MAX13108E
t
PVCC-VL
= t
PHL
or t
PLH
t
FVL
t
RVL
Figure 2a. Driving I/O V
CC_
Figure 2b. Timing for Driving I/O V
CC_
_______________________________________________________________________________________
5
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