74AHC08-Q100; 74AHCT08-Q100
Quad 2-input AND gate
Rev. 1 — 16 April 2013
Product data sheet
1. General description
The 74AHC08-Q100; 74AHCT08-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard JESD7-A.
The 74AHC08-Q100; 74AHCT08-Q100 provides the quad 2-input AND function.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accept voltages higher than V
CC
For 74AHC08-Q100 only: operates with CMOS input levels
For 74AHCT08-Q100 only: operates with TTL input levels
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AHC08D-Q100
74AHCT08D-Q100
74AHC08PW-Q100
74AHCT08PW-Q100
74AHC08BQ-Q100
74AHCT08BQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP14
40 C
to +125
C
SO14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
SOT762-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
NXP Semiconductors
74AHC08-Q100; 74AHCT08-Q100
Quad 2-input AND gate
4. Functional diagram
1
2
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
1Y
3
4
2Y
6
5
&
6
A
Y
&
8
B
mna221
&
3
3Y
8
9
10
4Y
11
12
&
mna222
11
13
mna223
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one gate)
5. Pinning information
5.1 Pinning
$+&4
$+&74
$
%
<
$
%
<
*1'
DDD
9
&&
%
$
<
%
$
<
%
<
$
%
<
*1'
9
&&
%
$
<
%
$
WHUPLQDO
LQGH[ DUHD
$+&4
$+&74
$
<
DDD
7UDQVSDUHQW WRS YLHZ
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
74AHC_AHCT08_Q100
All information provided in this document is subject to legal disclaimers.
*1'
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 April 2013
2 of 14
NXP Semiconductors
74AHC08-Q100; 74AHCT08-Q100
Quad 2-input AND gate
5.2 Pin description
Table 2.
Symbol
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
1Y, 2Y, 3Y, 4Y
GND
V
CC
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
6. Functional description
Table 3.
Input
nA
L
X
H
[1]
Function selection
[1]
Output
nB
X
L
H
nY
L
L
H
H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
SO14 package
TSSOP14 package
DHVQFN14 package
[1]
[2]
[3]
[4]
Conditions
Min
0.5
0.5
Max
+7.0
+7.0
-
20
25
75
-
+150
500
500
500
Unit
V
V
mA
mA
mA
mA
mA
C
mW
mW
mW
V
I
<
0.5
V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
20
-
-
-
75
65
T
amb
=
40 C
to +125
C
[2]
[3]
[4]
-
-
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 8 mW/K above 70
C.
P
tot
derates linearly with 5.5 mW/K above 60
C.
P
tot
derates linearly with 4.5 mW/K above 60
C.
74AHC_AHCT08_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 April 2013
3 of 14
NXP Semiconductors
74AHC08-Q100; 74AHCT08-Q100
Quad 2-input AND gate
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise
and fall rate
V
CC
= 3.3 V
0.3 V
V
CC
= 5.0 V
0.5 V
Conditions
74AHC08-Q100
Min
2.0
0
0
40
-
-
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
100
20
74AHCT08-Q100
Min
4.5
0
0
40
-
-
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
-
20
V
V
V
C
ns/V
ns/V
Unit
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
For type 74AHC08-Q100
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
OH
HIGH-level
V
I
= V
IH
or V
IL
output voltage
I
O
=
50 A;
V
CC
= 2.0 V
I
O
=
50 A;
V
CC
= 3.0 V
I
O
=
50 A;
V
CC
= 4.5 V
I
O
=
4.0
mA; V
CC
= 3.0 V
I
O
=
8.0
mA; V
CC
= 4.5 V
V
OL
LOW-level
V
I
= V
IH
or V
IL
output voltage
I
O
= 50
A;
V
CC
= 2.0 V
I
O
= 50
A;
V
CC
= 3.0 V
I
O
= 50
A;
V
CC
= 4.5 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
O
= 8.0 mA; V
CC
= 4.5 V
I
I
I
CC
C
I
input leakage
current
V
I
= V
CC
or GND; V
CC
=
5.5 V
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.0
3.0
4.5
-
-
0
0
0
-
-
-
-
3.0
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.36
0.36
0.1
2.0
10
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.48
3.8
-
-
-
-
-
-
-
-
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.44
0.44
1.0
20
10
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.4
3.7
-
-
-
-
-
-
-
-
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.55
0.55
2.0
40
10
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
A
pF
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
input
capacitance
74AHC_AHCT08_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 April 2013
4 of 14
NXP Semiconductors
74AHC08-Q100; 74AHCT08-Q100
Quad 2-input AND gate
Table 6.
Static characteristics
…continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
For type 74AHCT08-Q100
V
IH
V
IL
V
OH
HIGH-level
input voltage
LOW-level
input voltage
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V
2.0
-
-
-
-
0.8
2.0
-
-
0.8
2.0
-
-
0.8
V
V
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
HIGH-level
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
output voltage
I
O
=
50 A
I
O
=
8.0
mA
LOW-level
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
output voltage
I
O
= 50
A
I
O
= 8.0 mA
input leakage
current
V
I
= V
IH
or V
IL
; V
CC
= 5.5 V
4.4
3.94
-
-
-
-
-
4.5
-
0
-
-
-
-
-
-
0.1
0.36
0.1
2.0
1.35
4.4
3.8
-
-
-
-
-
-
-
0.1
0.44
1.0
20
1.5
4.4
3.7
-
-
-
-
-
-
-
0.1
0.55
2.0
40
1.5
V
V
V
V
A
A
mA
V
OL
I
I
I
CC
I
CC
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
additional
per input pin;
supply current V
I
= V
CC
2.1 V; I
O
= 0 A;
other pins at V
CC
or GND;
V
CC
= 4.5 V to 5.5 V
input
capacitance
C
I
-
3.0
10
-
10
-
10
pF
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; For test circuit see
Figure 7.
Symbol Parameter
Conditions
Min
For type 74AHC08-Q100
t
pd
propagation
delay
nA, nB to nY; see
Figure 6
V
CC
= 3.0 V to 3.6 V
C
L
= 15 pF
C
L
= 50 pF
V
CC
= 4.5 V to 5.5 V
C
L
= 15 pF
C
L
= 50 pF
C
PD
power
dissipation
capacitance
C
L
= 50 pF; f
i
= 1 MHz;
V
I
= GND to V
CC
[3]
[2]
25
C
Typ
[1]
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
-
-
-
-
4.0
5.6
3.0
4.2
10.0
8.8
12.3
5.9
7.9
-
1.0
1.0
1.0
1.0
-
10.5
14
7.0
9.0
-
1.0
1.0
1.0
1.0
-
11.0
15.5
7.5
10.0
-
ns
ns
ns
ns
pF
74AHC_AHCT08_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 April 2013
5 of 14
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