电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

74HC112D,652

产品描述Flip Flop JK-Type Neg-Edge 2-Element 16-Pin SO Bulk
文件大小716KB,共20页
制造商Nexperia
官网地址https://www.nexperia.com
下载文档 详细参数 选型对比 全文预览

74HC112D,652概述

Flip Flop JK-Type Neg-Edge 2-Element 16-Pin SO Bulk

74HC112D,652规格参数

参数名称属性值
欧盟限制某些有害物质的使用Compliant
ECCN (US)EAR99
Part StatusLTB
HTS8542.39.00.01
Logic FamilyHC
Logic FunctionJK-Type
Number of Channels per Chip2
Number of Elements per Chip2
Number of Element Inputs2
Number of Element Outputs1
Bus HoldNo
Set/ResetSet/Reset
PolarityInverting/Non-Inverting
Triggering TypeNegative-Edge
Maximum Propagation Delay Time @ Maximum CL (ns)175@2V|35@4.5V|30@6V
Absolute Propagation Delay Time (ns)270
Process TechnologyCMOS
Input Signal TypeSingle-Ended
Maximum Low Level Output Current (mA)7.8
Maximum High Level Output Current (mA)-7.8
Minimum Operating Supply Voltage (V)2
Typical Operating Supply Voltage (V)5
Maximum Operating Supply Voltage (V)6
Maximum Quiescent Current (mA)0.004
Propagation Delay Test Condition (pF)50
Minimum Operating Temperature (°C)-40
Maximum Operating Temperature (°C)125
系列
Packaging
Bulk
Supplier PackageSO
Pin Count16
MountingSurface Mount
Package Height1.45(Max)
Package Length10(Max)
Package Width4(Max)
PCB changed16

文档预览

下载PDF文档
74HC112; 74HCT112
Dual JK flip-flop with set and reset; negative-edge trigger
Rev. 3 — 9 August 2016
Product data sheet
1. General description
The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features
individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has
complementary nQ and nQ outputs. The set and reset are asynchronous active LOW
inputs and operate independently of the clock input. The J and K inputs control the state
changes of the flip-flops as described in the mode select function table. The J and K
inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for
predictable operation. Inputs include clamp diodes that enable the use of current limiting
resistors to interface inputs to voltages in excess of V
CC
.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features and benefits
Input levels:
For 74HC112: CMOS level
For 74HCT112: TTL level
Asynchronous set and reset
Specified in compliance with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC112D
74HCT112D
74HC112DB
74HCT112DB
74HC112PW
74HCT112PW
40 C
to +125
C
40 C
to +125
C
SSOP16
plastic shrink small outline package; 16 leads; body width
5.3 mm
SOT338-1
SOT403-1
40 C
to +125
C
Name
SO16
Description
Version
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Type number
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm

74HC112D,652相似产品对比

74HC112D,652 74HC112PW,118 74HC112D,653 74HC112PW,112
描述 Flip Flop JK-Type Neg-Edge 2-Element 16-Pin SO Bulk Flip Flop JK-Type Neg-Edge 2-Element 16-Pin TSSOP T/R Flip Flop JK-Type Neg-Edge 2-Element 16-Pin SO T/R Flip Flop JK-Type Neg-Edge 2-Element 16-Pin TSSOP Bulk
欧盟限制某些有害物质的使用 Compliant - Compliant Compliant
ECCN (US) EAR99 - EAR99 EAR99
Part Status LTB - Active LTB
HTS 8542.39.00.01 - 8542.39.00.01 8542.39.00.01
Logic Family HC - HC HC
Logic Function JK-Type - JK-Type JK-Type
Number of Channels per Chip 2 - 2 2
Number of Elements per Chip 2 - 2 2
Number of Element Inputs 2 - 2 2
Number of Element Outputs 1 - 1 1
Bus Hold No - No No
Set/Reset Set/Reset - Set/Reset Set/Reset
Polarity Inverting/Non-Inverting - Inverting/Non-Inverting Inverting/Non-Inverting
Triggering Type Negative-Edge - Negative-Edge Negative-Edge
Maximum Propagation Delay Time @ Maximum CL (ns) 175@2V|35@4.5V|30@6V - 175@2V|35@4.5V|30@6V 30@6V|35@4.5V|175@2V
Absolute Propagation Delay Time (ns) 270 - 270 270
Process Technology CMOS - CMOS CMOS
Input Signal Type Single-Ended - Single-Ended Single-Ended
Maximum Low Level Output Current (mA) 7.8 - 7.8 7.8
Maximum High Level Output Current (mA) -7.8 - -7.8 -7.8
Minimum Operating Supply Voltage (V) 2 - 2 2
Typical Operating Supply Voltage (V) 5 - 5 5
Maximum Operating Supply Voltage (V) 6 - 6 6
Maximum Quiescent Current (mA) 0.004 - 0.004 0.004
Propagation Delay Test Condition (pF) 50 - 50 50
Minimum Operating Temperature (°C) -40 - -40 -40
Maximum Operating Temperature (°C) 125 - 125 125
系列
Packaging
Bulk - Tape and Reel Bulk
Supplier Package SO - SO TSSOP
Pin Count 16 - 16 16
Mounting Surface Mount - Surface Mount Surface Mount
Package Height 1.45(Max) - 1.45(Max) 0.95(Max)
Package Length 10(Max) - 10(Max) 5.1(Max)
Package Width 4(Max) - 4(Max) 4.5(Max)
PCB changed 16 - 16 16

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 1445  1947  929  2781  706  17  46  30  34  12 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved