CAT24WC164
16K-Bit Serial EEPROM, Cascadable
FEATURES
I
400 kHz I
2
C bus compatible*
I
1.8 to 5.5 volt operation
I
Low power CMOS technology
I
Write protect feature
I
1,000,000 program/erase cycles
I
100 year data retention
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
I
Self-timed write cycle with auto-clear
I
8-pin DIP, 8-pin SOIC, 8-pin MSOP or
8 pin TSSOP
I
Industrial, automotive and
- Entire array protected when WP at V
IH
I
Page write buffer
(Also available in "Green" packages)
extended temperature ranges
DESCRIPTION
The CAT24WC164 is a16K-bit, cascadable Serial CMOS
EEPROM internally organized as 2048 words of 8 bits
each. Catalyst’s advanced CMOS technology substan-
tially reduces device power requirements. The
CAT24WC164 features a 16-byte page write buffer. The
device operates via the I
2
C bus serial interface, has a
special write protection feature, and is available in 8-pin
DIP, 8-pin SOIC, 8-pin TSSOP and 8-lead MSOP.
PIN CONFIGURATION
DIP Package (P, L)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
SOIC Package (J, W)
A0
A1
A2
VSS
MSOP Package (R, Z)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
PIN FUNCTIONS
Pin Name
A0, A1, A2
SDA
SCL
WP
V
CC
V
SS
i
D
VCC
TEST
SCL
SDA
c
s
A0
A1
A2
VSS
1
2
3
4
TSSOP Package (U, Y)
8
7
6
5
i
t
n
o
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
5020 FHD F01
u
n
VCC
VSS
SDA
VCC
WP
SCL
SDA WP
BLOCK DIAGRAM
EXTERNAL LOAD
d
e
START/STOP
LOGIC
CONTROL
LOGIC
a
P
XDEC
t
r
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
E
2
PROM
Function
DATA IN STORAGE
Device Address Inputs
HIGH VOLTAGE/
TIMING CONTROL
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
Serial Data/Address
Serial Clock
Write Protect
+1.8V to +5.5V Power Supply
Ground
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1026, Rev. J
CAT24WC164
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
........... –2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Max.
1,000,000
100
2000
100
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified.
Symbol
I
CC
I
SB(5)
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
Parameter
Power Supply Current
Standby Current (V
CC
= 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
I/O(3)
C
IN(3)
Parameter
Test Conditions
V
I/O
= 0V
V
IN
= 0V
Min
Typ
Max
8
6
Units
pF
pF
Input/Output Capacitance (SDA)
i
D
Output Low Voltage (V
CC
= 3.0V)
Output Low Voltage (V
CC
= 1.8V)
c
s
i
t
n
o
Test Conditions
f
SCL
= 100 kHz
V
IN
= GND or V
CC
V
IN
= GND to V
CC
u
n
d
e
Min
–1
a
P
Units
Cycles/Byte
Years
Volts
mA
Max
3
1
10
10
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.5
t
r
mA
µA
µA
µA
V
V
V
V
Typ
Units
V
OUT
= GND to V
CC
V
CC
x 0.7
I
OL
= 3 mA
I
OL
= 1.5 mA
Input Capacitance
(A0, A1, A2, SCL, WP)
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) Maximum standby current (I
SB
) = 10µA for the Automotive and Extended Automotive temperature range.
Doc. No. 1026, Rev. J
2
CAT24WC164
A.C. CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
1.8 V - 5.5 V
Min
F
SCL
T
I(1)
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
Clock Frequency
Noise Suppression Time
Constant at SCL, SDA Inputs
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
4.7
4
4.7
4
Max
100
200
3.5
1.2
2.5 V - 5.5 V
Min
Max
400
200
Units
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Power-Up Timing
(1)(2)
Symbol
t
PUR
t
PUW
Write Cycle Limits
Symbol
t
WR
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
i
D
c
s
Parameter
Parameter
Power-up to Read Operation
Power-up to Write Operation
i
t
n
o
u
n
0
50
4
100
4.7
d
e
1.2
0.6
0.6
0
50
1
300
0.6
100
Min
Typ
0.6
a
P
1
0.3
300
Max
1
1
t
r
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Units
ms
ms
Min
Typ
Max
5
Units
ms
Write Cycle Time
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
3
Doc. No. 1026, Rev. J
CAT24WC164
FUNCTIONAL DESCRIPTION
The CAT24WC164 supports the I
2
C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. Data transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC164
operates as a Slave device. Both the Master and Slave
devices can operate as either transmitter or receiver, but
the Master device controls which mode is activated. A
maximum of 8 devices may be connected to the bus as
determined by the device address inputs A0, A1, and A2.
PIN DESCRIPTIONS
SCL:
Serial Clock
The CAT24WC164 serial clock input pin is used to clock
all data transfers into or out of the device. This is an input
pin.
SDA:
Serial Data/Address
The CAT24WC164 bidirectional serial data/address pin
is used to transfer data into and out of the device. The
SDA pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
A0, A1, A2:
Device Address Inputs
These inputs set device address when cascading multiple
devices. When these pins are left floating the default
values are zeros.
A maximum of eight devices can be cascaded. If only
one CAT24WC164 is addressed on the bus, all three
Figure 1. Bus Timing
tF
tLOW
tHIGH
tLOW
tR
SCL
tSU:STA
SDA IN
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
Figure 3. Start/Stop Timing
i
D
c
s
8TH BIT
BYTE n
i
t
n
o
tHD:STA
tAA
ACK
tHD:DAT
u
n
tDH
tWR
tSU:DAT
d
e
a
P
tSU:STO
tBUF
t
r
STOP
CONDITION
START
CONDITION
ADDRESS
SDA
SCL
START BIT
STOP BIT
Doc. No. 1026, Rev. J
4
CAT24WC164
address pins (A0, A1and A2) can be left floating or
connected to V
SS
.
The CAT24WC164 can be made compatible with the
CAT24WC16 by tying A2, A1 and A0 to VSS or by
leaving A2, A1 and A0 float.
WP:
Write Protect
If the WP pin is tied to V
CC
the entire memory array
becomes Write Protected (READ only). When the WP
pin is tied to V
SS
or left floating normal read/write
operations are allowed to the device.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The most
significant bit of the 8-bit slave address is fixed as 1. (see
Fig. 5). The next three significant bits (A2, A1, A0) are
the device address bits and define which device or which
part of the device the Master is accessing (The A1 bit
must be the compliment of the A1 input pin signal). Up
to eight CAT24WC164 devices may be individually
addressed by the system. The next three bits are used
as the three most significant bits of the data word
address. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC164 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC164 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
I
2
C BUS PROTOCOL
The following defines the features of the I
2
C bus protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC164 monitor the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Figure 4. Acknowledge Timing
i
D
c
s
i
t
n
o
1
START
u
n
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowl-
edging device pulls down the SDA line during the ninth
clock cycle, signaling that it received the 8 bits of data.
The CAT24WC164 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
d
e
8
a
P
t
r
SCL FROM
MASTER
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
5
Doc. No. 1026, Rev. J
FPGA/CPLD
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