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74LVC14A-Q100
Hex inverting Schmitt trigger with 5 V tolerant input
Rev. 2 — 10 June 2016
Product data sheet
1. General description
The 74LVC14A-Q100 provides six inverting buffers with Schmitt trigger input. It is capable
of transforming slowly changing input signals into sharply defined, jitter-free output
signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage V
T+
and the negative voltage V
T
is defined as the input
hysteresis voltage V
H
.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device as a translator in mixed 3.3 V and 5 V applications.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide supply voltage range from 1.2 V to 3.6 V
5 V tolerant input for interfacing with 5 V logic
CMOS low-power consumption
Direct interface with TTL levels
Unlimited input rise and fall times
Inputs accept voltages up to 5.5 V
Complies with JEDEC standard JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Applications
Wave and pulse shapers for highly noisy environments
Astable multivibrators
Monostable multivibrators
NXP Semiconductors
74LVC14A-Q100
Hex inverting Schmitt trigger with 5 V tolerant input
4. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVC14AD-Q100
40 C
to +125
C
SO14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
SOT762-1
Type number
74LVC14APW-Q100
40 C
to +125
C
74LVC14ABQ-Q100
40 C
to +125
C
DHVQFN14 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
5. Functional diagram
1
2
1
1A
1Y
2
3
4
3
2A
2Y
4
5
6
5
3A
3Y
6
9
8
9
4A
4Y
8
11
5A
5Y
10
11
10
13
6A
6Y
12
13
12
mna204
001aac497
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
A
Y
mna025
Fig 3.
Logic diagram for one Schmitt trigger
74LVC14A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 2 — 10 June 2016
2 of 17
NXP Semiconductors
74LVC14A-Q100
Hex inverting Schmitt trigger with 5 V tolerant input
6. Pinning information
6.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
6.2 Pin description
Table 2.
Symbol
1A, 2A, 3A, 4A, 5A, 6A
1Y, 2Y, 3Y, 4Y, 5Y, 6Y
GND
V
CC
Pin description
Pin
1, 3, 5, 9, 11, 13
2, 4, 6, 8, 10, 12
7
14
Description
data input
data output
ground (0 V)
supply voltage
7. Functional description
Table 3.
Input nA
L
H
[1]
H = HIGH voltage level; L = LOW voltage level
Function table
[1]
Output nY
H
L
74LVC14A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 2 — 10 June 2016
3 of 17
NXP Semiconductors
74LVC14A-Q100
Hex inverting Schmitt trigger with 5 V tolerant input
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
[1]
[2]
Min
0.5
0.5
0.5
50
-
-
-
100
65
Max
+6.5
+6.5
V
CC
+ 0.5
-
50
50
100
-
+150
500
Unit
V
V
V
mA
mA
mA
mA
mA
C
mW
V
I
< 0 V
V
O
> V
CC
or V
O
< 0 V
V
O
= 0 V to V
CC
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO14 packages: P
tot
derates linearly with 8 mW/K above 70
C.
For TSSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN14 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
9. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
T
amb
Recommended operating conditions
Parameter
supply voltage
functional
input voltage
output voltage
ambient temperature
Conditions
Min
1.65
1.2
0
0
40
Typ
-
-
-
-
-
Max
3.6
-
5.5
V
CC
+125
Unit
V
V
V
V
C
74LVC14A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 2 — 10 June 2016
4 of 17
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