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74LVC163
Presettable synchronous 4-bit binary counter; synchronous
reset
Rev. 6 — 20 November 2012
Product data sheet
1. General description
The 74LVC163 is a synchronous presettable binary counter which features an internal
look-ahead carry and can be used for high-speed counting. Synchronous operation is
provided by having all flip-flops clocked simultaneously on the positive-going edge of the
clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a HIGH-level
or LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting
action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter
on the positive-going edge of the clock (provided that the set-up and hold time
requirements for PE are met). Preset takes place regardless of the levels at count enable
inputs (pin CEP and CET). A LOW-level at the master reset input (pin MR) sets all four
outputs of the flip-flops (pins Q0 to Q3) to LOW-level after the next positive-going
transition on the clock input (pin CP) (provided that the set-up and hold time requirements
for PE are met). This action occurs regardless of the levels at input pins PE, CET and
CEP. This synchronous reset feature enables the designer to modify the maximum count
with only one external NAND gate.
The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs
(pin CEP and CET) must be HIGH in count. The CET input is fed forward to enable the
terminal count output (pin TC). The TC output thus enabled will produce a HIGH output
pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be
used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters is determined by t
PHL
(propagation delay CP to TC) and t
su
(set-up time CEP to CP) according to the formula:
1
f
max
=
----------------------------------- .
t
PHL
max
+
t
su
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Synchronous reset
Synchronous counting and loading
Two count enable inputs for n-bit cascading
Positive edge-triggered clock
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
NXP Semiconductors
74LVC163
Presettable synchronous 4-bit binary counter; synchronous reset
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to 125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC163D
74LVC163DB
74LVC163PW
74LVC163BQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO16
SSOP16
TSSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
SOT763-1
Type number
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
4. Functional diagram
1
15
TC
3
4
5
6
9
D0
D1
D2
D3
PE
CEP CET
7
10
CP
2
MR
1
mna905
Q0
Q1
Q2
Q3
14
13
12
11
3
4
5
6
4 CT = 15
mna906
R
M1
G3
G4
CTR4
9
7
10
2
C2/1,3,4+
1,2D
14
13
12
11
15
Fig 1.
Logic diagram
Fig 2.
IEC logic symbol
74LVC163
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 20 November 2012
2 of 20
NXP Semiconductors
74LVC163
Presettable synchronous 4-bit binary counter; synchronous reset
3
D0
9
10
7
2
1
PE
CET
4
D1
5
D2
6
D3
0
15
15
14
13
6
7
11
10
9
8
mna908
PARALLEL LOAD
CIRCUITRY
1
2
3
4
5
TC
CEP
CP
MR
BINARY
COUNTER
Q0
14
Q1
13
Q2
12
Q3
mna907
12
11
Fig 3.
Functional diagram
Fig 4.
State diagram
MR
PE
D0
D1
D2
D3
CP
CEP
CET
Q0
Q1
Q2
Q3
TC
12
RESET PRESET
13
14
15
0
1
2
INHIBIT
mgu760
COUNT
Typical timing sequence: Reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and two;
inhibit.
Fig 5.
Timing sequence
74LVC163
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 20 November 2012
3 of 20
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Product data sheet
Rev. 6 — 20 November 2012
4 of 20
74LVC163
NXP Semiconductors
D0
D1
D2
D3
CET
CEP
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Presettable synchronous 4-bit binary counter; synchronous reset
PE
MR
D
CP
FF0
Q
D
FF1
Q
D
FF2
Q
D
FF3
Q
CP
Q
CP
Q
CP
Q
CP
Q
74LVC163
Q0
Q1
Q2
Q3
TC
mgu761
Fig 6.
Logic diagram
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