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74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
Rev. 8 — 29 March 2013
Product data sheet
1. General description
The 74LVC2T45; 74LVCH2T45 are dual bit, dual supply translating transceivers with
3-state outputs that enable bidirectional level translation. They feature two 2-bits
input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (V
CC(A)
and V
CC(B)
). Both V
CC(A)
and V
CC(B)
can be supplied at any voltage between 1.2 V and
5.5 V making the device suitable for translating between any of the low voltage nodes
(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins nA and DIR are referenced to V
CC(A)
and
pins nB are referenced to V
CC(B)
. A HIGH on DIR allows transmission from nA to nB and a
LOW on DIR allows transmission from nB to nA.
The devices are fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either V
CC(A)
or V
CC(B)
are at
GND level, both A port and B port are in the high-impedance OFF-state.
Active bus hold circuitry in the 74LVCH2T45 holds unused or floating data inputs at a valid
logic level.
2. Features and benefits
Wide supply voltage range:
V
CC(A)
: 1.2 V to 5.5 V
V
CC(B)
: 1.2 V to 5.5 V
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 4000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Maximum data rates:
420 Mbps (3.3 V to 5.0 V translation)
210 Mbps (translate to 3.3 V))
140 Mbps (translate to 2.5 V)
75 Mbps (translate to 1.8 V)
60 Mbps (translate to 1.5 V)
NXP Semiconductors
74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
24
mA output drive (V
CC
= 3.0 V)
Inputs accept voltages up to 5.5 V
Low power consumption: 16
A
maximum I
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC2T45DC
74LVCH2T45DC
74LVC2T45GT
74LVCH2T45GT
74LVC2T45GF
74LVCH2T45GF
74LVC2T45GD
74LVCH2T45GD
74LVC2T45GM
74LVCH2T45GM
74LVC2T45GN
74LVCH2T45GN
74LVC2T45GS
74LVCH2T45GS
40 C
to +125
C
XSON8
40 C
to +125
C
XSON8
40 C
to +125
C
XQFN8
40 C
to +125
C
XSON8
40 C
to +125
C
XSON8
40 C
to +125
C
XSON8
40 C
to +125
C
Name
VSSOP8
Description
Version
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1
1.95
0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
1
0.5 mm
SOT1089
Type number
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; body 3
2
0.5 mm
plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6
1.6
0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.2
1.0
0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
1.0
0.35 mm
SOT902-2
SOT1116
SOT1203
4. Marking
Table 2.
Marking
Marking code
[1]
V45
X45
V45
X45
V5
X5
V45
X45
V45
X45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Type number
74LVC2T45DC
74LVCH2T45DC
74LVC2T45GT
74LVCH2T45GT
74LVC2T45GF
74LVCH2T45GF
74LVC2T45GD
74LVCH2T45GD
74LVC2T45GM
74LVCH2T45GM
74LVC_LVCH2T45
Product data sheet
Rev. 8 — 29 March 2013
2 of 36
NXP Semiconductors
74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
Table 2.
Marking
…continued
Marking code
[1]
V5
X5
V5
X5
Type number
74LVC2T45GN
74LVCH2T45GN
74LVC2T45GS
74LVCH2T45GS
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
DIR
5
DIR
1A
2
1A
7
1B
1B
2A
3
2A
6
V
CC(A)
V
CC(B)
V
CC(A)
001aag577
2B
2B
V
CC(B)
001aag578
Fig 1.
Logic symbol
Fig 2.
Logic diagram
6. Pinning information
6.1 Pinning
74LVC2T45
74LVCH2T45
V
CC(A)
1
8
V
CC(B)
1A
2
7
1B
74LVC2T45
74LVCH2T45
2A
V
CC(A)
1A
2A
GND
1
2
3
4
001aai904
3
6
2B
8
7
6
5
V
CC(B)
1B
2B
DIR
GND
4
5
DIR
001aai905
Transparent top view
Fig 3.
Pin configuration SOT765-1
Fig 4.
Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
3 of 36
NXP Semiconductors
74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
74LVC2T45
74LVCH2T45
terminal 1
index area
V
CC(B)
1
8
74LVC2T45
74LVCH2T45
V
CC(A)
1A
2A
GND
1
2
3
4
8
7
6
5
V
CC(B)
1B
7
V
CC(A)
2B
1B
2B
DIR
DIR
2
6
1A
3
4
5
2A
GND
001aai906
001aaj617
Transparent top view
Transparent top view
Fig 5.
Pin configuration SOT996-2
Fig 6.
Pin configuration SOT902-2
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SOT765-1, SOT833-1, SOT1089,
SOT996-2, SOT1116 and SOT1203
V
CC(A)
1A
2A
GND
DIR
2B
1B
V
CC(B)
1
2
3
4
5
6
7
8
SOT902-2
7
6
5
4
3
2
1
8
supply voltage A (port A and DIR)
data input or output
data input or output
ground (0 V)
direction control
data input or output
data input or output
supply voltage B (port B)
Description
7. Functional description
Table 4.
Function table
[1]
Input
DIR
L
H
X
Input/output
[2]
nA
nA = nB
input
Z
nB
input
nB = nA
Z
Supply voltage
V
CC(A)
, V
CC(B)
1.2 V to 5.5 V
1.2 V to 5.5 V
GND
[3]
[1]
[2]
[3]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
The input circuit of the data I/O is always active.
When either V
CC(A)
or V
CC(B)
is at GND level, the device goes into suspend mode.
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
4 of 36
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