The UT28F64LV amorphous silicon anti-fuse PROM is a high
performance, asynchronous, radiation-hardened,
8K x 8 programmable memory device. The UT28F64LV PROM
features fully asychronous operation requiring no external clocks
or timing strobes. An advanced radiation-hardened twin-well
CMOS process technology is used to implement the
UT28F64LV. The combination of radiation- hardness, fast
access time, and low power consumption make the UT28F64LV
ideal for high speed systems designed for operation in radiation
environments.
A(12:0)
DECODER
MEMORY
ARRAY
SENSE AMPLIFIER
CE
PE
OE
PROGRAMMING
CONTROL
LOGIC
DQ(7:0)
Figure 1. PROM Block Diagram
1
DEVICE OPERATION
The UT28F64LV has three control inputs: Chip Enable (CE),
Program Enable (PE), and Output Enable (OE); thirteen address
inputs, A(12:0); and eight bidirectional data lines, DQ(7:0). CE
is the device enable input that controls chip selection, active, and
standby modes. Asserting CE causes I
DD
to rise to its active value
and decodes the thirteen address inputs to select one of 8,192
words in the memory. PE controls program and read operations.
During a read cycle, OE must be asserted to enable the outputs.
PIN CONFIGURATION
PIN NAMES
A(12:0)
CE
OE
PE
DQ(7:0)
Address
Chip Enable
Output Enable
Program Enable
Data Input/Data Output
Table 1. Device Operation Truth Table
1
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
PE
NC
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
OE
X
0
1
1
PE
1
1
0
1
CE
1
0
0
0
I/O MODE
Three-state
Data Out
Data In
Three-state
MODE
Standby
Read
Program
Read
2
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD
V
I/O
T
STG
P
D
T
J
Θ
JC
I
I
PARAMETER
DC supply voltage
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
Thermal resistance, junction-to-case
2
DC input current
LIMITS
-0.3 to 7.0
-0.5 to (V
DD
+ 0.5)
-65 to +150
1.5
+175
3.3
UNITS
V
V
°C
W
°C
°C/W
mA
±
10
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
2. Test per MIL-STD-883, Method 1012, infinite heat sink.
2
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
T
C
V
IN
PARAMETER
Positive supply voltage
Case temperature range
DC input voltage
LIMITS
3.0 to 3.6
-55 to +125
0 to V
DD
UNITS
V
°C
V
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(V
DD
= 3.0V to 3.6V; -55°C < T
C
< +125°C)
SYMBOL
V
IH
V
IL
V
OL
1
V
OL
2
V
OH
1
V
OH
2
C
IN 1
C
IO 1, 4
I
IN
I
OZ
PARAMETER
High-level input voltage
Low-level input voltage
Low-level output voltage
Low-level output voltage
High-level output voltage
High-level output voltage
Input capacitance
Bidirectional I/O capacitance
I
OL
= 100µA, V
DD
= 3.0V
I
OL
= 1.0mA, V
DD
= 3.0V
I
OH
= -100µA, V
DD
= 3.0V
I
OH
= -1.0mA V
DD
= 3.0V
ƒ
= 1MHz, V
DD
= 3.3V
ƒ
= 1MHz, V
DD
= 3.3V
V
OUT
= 0V
Input leakage current
Three-state output leakage
current
V
IN
= 0V to V
DD
V
O
= 0V to V
DD
V
DD
= 3.6V
OE = 3.6V
V
DD
= 3.6V, V
O
= V
DD
V
DD
= 3.6V, V
O
= 0V
CMOS input levels (I
OUT
= 0),
V
IL
= 0.2V, V
IH
= 3.0V
V
DD
, PE = 3.6V
I
DD
(SB)
post-rad
Supply current standby
CMOS input levels,
V
IL
= V
SS
+0.25V
CE = V
DD
-025, V
IH
= V
DD
-0.25V
500
µA
50
mA
-3
-8
3
8
µA
µA
V
DD
- 0.15
V
DD
- 0.3
15
15
CONDITION
MINIMUM
.7V
DD
.25V
DD
V
SS
+ 0.05
V
SS
+ 0.1
MAXIMUM
UNIT
V
V
V
V
V
V
pF
pF
I
OS 2,3
I
DD
(OP)
5
Short-circuit output current
90
-90
mA
mA
Supply current operating
@18.2MHz (55ns product)
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si).
1. Measured only for initial qualification, and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. Functional test.
5. Derates at 1.5mA/MHz.
3
READ CYCLE
A combination of PE greater than V
IH
(min), and CE less than
V
IL
(max) defines a read cycle. Read access time is measured
from the latter of device enable, output enable, or valid address
to valid data output.
An address access read is initiated by a change in address inputs
while the chip is enabled with OE asserted and PE deasserted.
Valid data appears on data output, DQ(7:0), after the specified
t
AVQV
is satisfied. Outputs remain active throughout the entire
cycle. As long as device enable and output enable are active, the
address inputs may change at a rate equal to the minimum read
cycle time.
AC CHARACTERISTICS READ CYCLE (Post-Radiation)*
(V
DD
= 3.0V to 3.6V; -55°C < T
C
< +125°C)
SYMBOL
t
AVAV1
t
AVQV
t
AXQX2
t
GLQX2
t
GLQV
t
GHQZ
t
ELQX2
t
ELQV
t
EHQZ
PARAMETER
Read cycle time
Read access time
Output hold time
OE-controlled output enable time
OE-controlled access time
OE-controlled output three-state time
CE-controlled output enable time
CE-controlled access time
CE-controlled output three-state time
The chip enable-controlled access is initiated by CE going active
while OE remains asserted, PE remains deasserted, and the
addresses remain stable for the entire cycle. After the specified
t
ELQV
is satisfied, the eight-bit word addressed by A(12:0)
appears at the data outputs DQ(7:0).
Output enable-controlled access is initiated by OE going active
while CE is asserted, PE is deasserted, and the addresses are
stable. Read access time is t
GLQV
unless t
AVQV
or t
ELQV
have
not been satisfied.
28F64-55
MIN
MAX
55
55
0
0
25
25
0
55
25
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si).
1. Functional test.
2. Three-state is defined as a 400mV change from steady-state output voltage.
4
t
AVAV
A(12:0)
CE
t
ELQX
t
ELQV
OE
t
GLQV
DQ(7:0)
t
GLQX
t
AVQV
t
AXQX
t
GHQZ
t
AVQV
t
EHQZ
Figure 2. PROM Read Cycle
RADIATION HARDNESS
The UT28F64LV PROM incorporates special design and layout
features which allow operation in high-level radiation
environments. UTMC has developed special low-temperature
processing techniques designed to enhance the total-dose
radiation hardness of both the gate oxide and the field oxide while
据外媒报道，萨里大学（University of Surrey）的研究人员开发出一种无需依赖GPS即可在人口密集的城市地区精确定位设备位置的人工智能系统。该系统可将定位误差从734米缩小到22米以内，这对于自动驾驶汽车和救援车辆等技术的发展意义重大。 图片来源： 萨里大学 在发表于《IEEE Robotics and Automation Letters》的论文中，研究人员介绍了PEn...[详细]
与云数据库相比，小型计算机是专门为网络边缘的去中心化坚固计算而构建的。通过将应用程序、分析和处理服务移动到更靠近数据生成源的位置，业务运营可以获得改进的实时计算应用程序性能。 l 从奔腾到酷睿i5的可扩展CPU性能 l 智能电源点火管理和CAN总线网络支持 l 无线局域网和广域网LTE连接 l 丰富的I/O可扩展性，包括PoE、PCI、PCIe、COM l 适用于宽工作温度和宽电压输入的坚固...[详细]
创意市集
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
