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7202LA50P

产品描述PDIP-28, Tube
产品类别存储    存储   
文件大小249KB,共15页
制造商IDT (Integrated Device Technology)
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7202LA50P概述

PDIP-28, Tube

7202LA50P规格参数

参数名称属性值
Brand NameIntegrated Device Technology
是否无铅含铅
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
零件包装代码PDIP
包装说明0.600 INCH, PLASTIC, DIP-28
针数28
制造商包装代码PD28
Reach Compliance Codenot_compliant
ECCN代码EAR99
最长访问时间50 ns
其他特性RETRANSMIT
最大时钟频率 (fCLK)15 MHz
周期时间65 ns
JESD-30 代码R-PDIP-T28
JESD-609代码e0
长度36.576 mm
内存密度9216 bit
内存集成电路类型OTHER FIFO
内存宽度9
湿度敏感等级1
功能数量1
端子数量28
字数1024 words
字数代码1000
工作模式ASYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织1KX9
可输出NO
封装主体材料PLASTIC/EPOXY
封装代码DIP
封装等效代码DIP28,.6
封装形状RECTANGULAR
封装形式IN-LINE
并行/串行PARALLEL
峰值回流温度(摄氏度)245
电源5 V
认证状态Not Qualified
座面最大高度4.699 mm
最大待机电流0.0005 A
最大压摆率0.08 mA
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn85Pb15)
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度15.24 mm
Base Number Matches1

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CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
IDT7200L
IDT7201LA
IDT7202LA
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
FEATURES:
First-In/First-Out dual-port memory
256 x 9 organization (IDT7200)
512 x 9 organization (IDT7201)
1,024 x 9 organization (IDT7202)
Low power consumption
— Active: 440mW (max.)
—Power-down: 28mW (max.)
Ultra high speed—12ns access time
Asynchronous and simultaneous read and write
Fully expandable by both word depth and/or bit width
720x family is pin and functionally compatible from 256 x 9 to 64k x 9
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
High-performance CEMOS™ technology
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing #5962-87531, 5962-89666, 5962-89863
and 5962-89536 are listed on this function
Dual versions available in the TSSOP package. For more informa-
tion, see IDT7280/7281/7282 data sheet
IDT7280 = 2 x IDT7200
IDT7281 = 2 x IDT7201
IDT7282 = 2 x IDT7202
Industrial temperature range (–40
o
C to +85
o
C) is available
(plastic packages only)
Green parts available, see ordering information
DESCRIPTION:
The IDT7200/7201/7202 are dual-port memories that load and empty data
on a first-in/first-out basis. The devices use Full and Empty flags to prevent data
overflow and underflow and expansion logic to allow for unlimited expansion
capability in both word size and depth.
The reads and writes are internally sequential through the use of ring
pointers, with no address information required to load and unload data. Data
is toggled in and out of the devices through the use of the Write (W) and Read
(R) pins.
The devices utilize a 9-bit wide data array to allow for control and parity bits
at the user’s option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (RT) capability that allows for reset
of the read pointer to its initial position when
RT
is pulsed LOW to allow for
retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
These FIFOs are fabricated using high-speed CMOS technology. They
are designed for those applications requiring asynchronous and simultaneous
read/writes in multiprocessing and rate buffer applications. Military grade
product is manufactured in compliance with MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(D
0
-D
8
)
W
WRITE
CONTROL
WRITE
POINTER
RAM
ARRAY
256 x 9
512 x 9
1,024 x 9
READ
POINTER
R
READ
CONTROL
THREE-
STATE
BUFFERS
DATA OUTPUTS
(Q
0
-Q
8
)
RS
RESET
LOGIC
FL/RT
FLAG
LOGIC
EXPANSION
LOGIC
EF
FF
XI
XO/HF
2679 drw 01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES
1
©2017
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2017
DSC-2679/15
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