NJU26123
■
General Description
Digital Signal Processor for TV
■
Package
The NJU26123 is a high performance 24-bit digital signal processor.
The NJU26123 provides ‘NJRC Original Sound Enhancement’, ‘Lip
sync Audio
Delay’,
10band PEQ, HPF/LPF (FIR Filter), DRC, Tone Control, and Clipper.
These kinds of sound functions are suitable for TV, mini-component, CD
radio-cassette, speakers system and other audio products.
■
FEATURES
- Software
•
NJRC Original Sound Enhancement (3D sound, Dialogue Boost, Bass Enhance)
•
Delay for Lip sync Audio Delay
( fs=48kHz : Max. 36msec, fs=44.1kHz : Max. 39msec, fs=32kHz : Max. 54msec )
•
10Band PEQ
•
HPF/LPF (FIR Filter)
•
DRC (Dynamic Range Compression) : 2-bands independent operation
•
Tone Control
•
Clipper
•
Master Volume
•
WatchDog Clock Output
NJU26123V
- Hardware
•
24bit Fixed-point Digital Signal Processing
•
Maximum System Clock Frequency : 12.288MHz Max. built-in PLL Circuit
•
Digital Audio Interface
: 3 Input ports / 3 Output ports
•
Digital Audio Format
: I
2
S 24bit, Left- justified, Right-justified, BCK : 32/64fs
•
Master / Slave Mode
- Master Mode, MCK : 384fs @32kHz, 256fs @48kHz
•
Host Interface
: I
2
C bus (Fast-mode/400kbps)
•
Power Supply
: 3.3V
•
Input terminal
: 5V Input tolerant
•
Package
: SSOP24 (Pb-Free)
Ver.2008-04-17
-1-
NJU26123
■
Function Block Diagram
SCL
I C INTERFACE
SDA
PROGRAM
CONTROL
24Bit x 24Bit
MULTIPLIER
ALU
TIMING
GENERATOR /
PLL
ADDRESS GENERATION UNIT
SERIAL AUDIO
INTERFACE
SDO0-2
BCK
LR
2
24Bit Fixed-point DSP Core
SDI0-2
RESETb
MCK
CLKOUT
CLK
SLAVEb
Internal Pow er
(1.8V)
WDC
FIRMWARE
ROM
GPIO
INTERFACE
PROC
AD1
Built-in LDO
VREGO
External
Low -ESR
Capacitors
Required
DATA RAM
1.8V level terminal
Fig. 1 NJU26123 Block Diagram
-2-
Ver.2008-04-17
NJU26123
■
DSP Block Diagram
SDI0
SDI1
SDI2
NJRC
Original Sound
Enhancement
EXEC Volume &
L/R Trimmer
Input Trimmer
Delay
PEQ
SW1
Tone Control
SW2
SW4 (DRC enable / disable)
HPF
EXEC Output
LPF
SW
DRC(HPF)
SW
SW
HPF Output
LPF Output
DRC Mixer
SW
SW
PROC Output
DRC(LPF)
SW
SW3 (DRC XOVER enable / disable)
C/SW Mixer
C/SW Output
EXEC Output
HPF Output
LPF Output
PROC Output
C/SW Output
SDO0/1/2
Source Select
SDO0
SDO0
Clipper (L/R)
SDO0
SW5
SDO1
Master Volume &
Channel Trimmer
SDO1
Clipper (R)
SDO1
SW6
SDO2
SDO2
SDO2
Fig. 2 NJU26123 Function Diagram
Ver.2008-04-17
-3-
NJU26123
■
Pin Configuration
RESETb
LR
BCK
SDI2
SDI1
SDI0
MCK
VDD
VSS
STBYb
VSS
VREGO
1
2
3
4
5
6
7
8
9
10
11
12
NJU26123
24
23
22
21
20
19
18
17
16
15
14
13
TEST
SCL
SDA
SDO2
SDO1
SDO0
WDC
PROC
AD1
SLAVEb
CLK
CLKOUT
SSOP24
Fig. 3 NJU26123 Pin Configuration
■
Pin Description
Table 1 Pin Description
No. Symbol
I/O Description
No. Symbol
I/O Description
1
RESETb I
RESET (active Low)
13
CLKOUT
O
OSC Output
2
LR
I/O LR Clock
14
CLK
I
OSC Clock Input
3
BCK
I/O Bit Clock
15
SLAVEb
I
Slave select
4
SDI2
I
Audio Data Input 2 L/R
16
AD1
I
I
2
C Address
5
SDI1
I
Audio Data Input 1 L/R
17
PROC
I
Status select after Reset DSP
6
SDI0
I
Audio Data Input 0 L/R
18
WDC
OD Clock for Watch Dog Timer
7
MCK
I/O Master Clock
19
SDO0
O
Audio Data Output 0 L/R
8
VDD
-
Power Supply +3.3V
20
SDO1
O
Audio Data Output 1 L/R
9
VSS
-
GND
21
SDO2
O
Audio Data Output 2 L/R
10
STBYb
I
For TEST (Connected to VDD)
22
SDA
OD I
2
C I/O
11
VSS
-
GND
23
SCL
I
I
2
C Clock
12
VREGO PI
Built-in Power Supply Bypass
24
TEST
I
For TEST(Connected to VSS)
* I : Input, O : Output, I/O: Bi-directional, OD: Open-Drain I/O, PI: Power Supply Bypass
AD1 (No.16) pin and PROC (No.17) pin are input pins. WDC (No.18) pin is open-drain pin with pull-up resistance.
However, these pins operate as bi-directional pins. No.16pin and No.17pin connect with V
DD
or V
SS
through 3.3kΩ
resistance. No.18pin do not connect or connect with V
DD
through 3.3kΩ resistance when unused.
VREGO (No.12) pin is a built-in power supply bypass pin. Connect low-ESR capacitor of 4.7uF and 0.01uF in parallel
between VSS (No.11) pin. A built-in power supply is used only for NJU26123 operation. Be not short-circuited of this pin.
Do not take out the current, and connect other power supplies.
-4-
Ver.2008-04-17
NJU26123
■
Absolute Maximum Ratings
( V
SS
=0V=GND, Ta=25°C )
°
Rating
Units
Table 2 Absolute Maximum Ratings
Parameter
Symbol
Supply Voltage *
Supply Voltage Bypass *
In
I/O, OD
Pin Voltage *
Out
CLK
CLKOUT
Power Dissipation
Operating Voltage
Storage Temperature
V
DD
V
REGO
V
x(IN)
V
x(I/O)
,V
x(OD)
V
x(OUT)
V
x(CLK)
V
x(CLKOUT)
-0.3 to 4.2
-0.3 to 2.3
-0.3 to 5.5 (V
DD
≥
3.0V)
-0.3 to 4.2 (V
DD
< 3.0V)
V
V
V
-0.3 to 4.2
565
mW
P
D
-40 to 85
T
OPR
°C
T
STR
-40 to 125
°C
* The LSI must be used inside of the “Absolute maximum ratings”. Otherwise, a stress may cause permanent
damage to the LSI.
* V
DD
: 8 pin
* V
REGO
: 12 pin
* V
x(IN)
: 1, 4, 5, 6, 10, 15, 23, 24 pin
* V
x(OD)
: 22 pin
* V
x(I/O)
: 2, 3, 7, 16, 17, 18 pin
* V
x(OUT)
: 19, 20, 21 pin
* V
x(CLK)
: 14 pin
* V
x(CLKOUT)
: 13 pin
V
DD
V
DD
(1.8V)
V
DD
V
DD
(1.8V)
■
Terminal equivalent circuit diagram
PAD
R
PD
CLK
CLKOUT
SS
Input, I/O (Input part)
(1 to 7, 22, 23pin)
(with R
PU
: 18pin , With R
PD
: 15, 16, 17, 24pin)
V
V
SS
CLK/CLKOUT
(13, 14pin)
V
DD
R
PU
PAD
Output Disable
PAD
V
DD
Output, I/O (Output part)
(2, 3, 7, 16, 17, 19, 20, 21pin )
( Open Drain Output with R
PU
: 18pin)
( Open Drain Output: 22pin )
V
SS
V
SS
STBYb
(10pin)
Fig.4 NJU26123 Terminal equivalent circuit diagram
Ver.2008-04-17
-5-
嵌入式系统
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