AMIS-30521, NCV70521
Micro-Stepping Motor Driver
Introduction
The AMIS−30521/NCV70521 is a micro−stepping stepper motor
driver for bipolar stepper motors. The chip is connected through I/O
pins and a SPI interface with an external microcontroller. The
AMIS−30521/NCV70521 contains a current−translation table. It takes
the next micro−step depending on the clock signal on the “NXT” input
pin and the status of the “DIR” (= direction) register or input pin. The
chip provides a so−called “Speed and Load Angle” output. This allows
the creation of stall detection algorithms and control loops based on
load−angle to adjust torque and speed. It is using a proprietary PWM
algorithm for reliable current control.
The AMIS−30521/NCV70521 is implemented in I
2
T100
technology, enabling both high voltage analog circuitry and digital
functionality on the same chip. The chip is fully compatible with the
automotive voltage requirements.
The 521 is ideally suited for general purpose stepper motor
applications in the automotive, industrial, medical and marine
environment. The AMIS−30521 is intended for use in industrial
applications. The NCV70521 version is qualified for use in
automotive applications.
Features
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PINOUT
MOTXP
26
VBB
MOTXP
25
24 GND
23 GND
22 MOTXN
21 MOTXN
20 MOTYN
19 MOTYN
18 GND
17 GND
9
CPN
10
CPP
11
VCP
12
CLR
13
CS
14
VBB
15
MOTYP
16
MOTYP
PC20070309.2
DO
TSTO
30
29
28
VDD
32
GND
DI
CLK
NXT
DIR
ERR
SLA
1
2
3
4
5
6
7
8
31
27
•
Dual H−Bridge for 2 Phase Stepper Motors
•
Programmable Peak−Current Up to 1.2 A Continuous (1.5 A Short
•
•
•
•
•
•
•
•
•
•
•
•
•
Time), Using a 5−Bit Current DAC
On−Chip Current Translator
SPI Interface
Speed and Load−Angle Output
7 Step Modes from Full Step−up to 32 Micro−Steps
Fully Integrated Current−Sense
PWM Current Control with Automatic Selection of Fast and Slow
Decay
Low EMC PWM with Selectable Voltage Slopes
Active Flyback Diodes
Full Output Protection and Diagnosis
Thermal Warning and Shutdown
Digital IO’s Compatible with 5 V and 3.3 V Microcontrollers
NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
These are Pb−Free Devices*
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 26 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2009
December, 2009
−
Rev. 2
1
Publication Order Number:
AMIS−30521/D
AMIS−30521, NCV70521
Table of Contents
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 4
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Equivalent Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . 5
Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operation Conditions . . . . . . . . . . . . . . . . 5
Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . 10
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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AMIS−30521, NCV70521
VDD
CPN CPP VCP
VBB
CLK
Timebase
Charge Pump
POR
CS
TRANSLATOR
DI
DO
NXT
DIR
SLA
Temp.
Sense
CLR
ERR
HV20081114.3
Logic &
Registers
Load
Angle
SPI
OTP
EMC
PWM
MOTXP
I−sense
MOTXN
EMC
PWM
MOTYP
I−sense
MOTYN
Band− AMIS−30521/NCV70521
gap
TST0
GND
Figure 1. Block Diagram AMIS−30521/NCV70521
Table 1. PIN DESCRIPTION
Name
GND
DI
CLK
NXT
DIR
ERR
SLA
/
CPN
CPP
VCP
CLR
CS
VBB
MOTYP
GND
MOTYN
MOTXN
GND
MOTXP
VBB
/
TST0
/
DO
VDD
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15, 16
17, 18
19, 20
21, 22
23, 24
25, 26
27
28
29
30
31
32
Ground
SPI Data In
SPI Clock Input
Next Micro−Step Input
Direction Input
Error Output (Open Drain)
Speed Load Angle Output
No Function (to be Tied to Ground)
Negative Connection of Charge Pump Capacitor
Positive Connection of Charge Pump Capacitor
Charge−Pump Filter−Capacitor
“Clear” = Chip Reset Input
SPI Chip Select Input
High Voltage Supply Input
Positive End of Phase Y Coil Output
Ground
Negative End of Phase Y coil Output
Negative End of Phase X coil Output
Ground
Positive End of Phase X Coil Output
High Voltage Supply Input
No Function (Has to be Left Open in Normal Condition)
Test pin input (to be Tied to Ground in Normal Operation)
No Function (to be Tied to Ground)
SPI Data Output (Open Drain)
Logic Supply Input (Needs External Decoupling Capacitor)
Digital Output
Supply
Type 4
Type 3
Digital Input
High Voltage
High Voltage
High Voltage
Digital Input
Digital Input
Supply
Driver Output
Supply
Driver Output
Driver Output
Supply
Driver Output
Supply
Type 3
Type 1
Type 2
Type 3
Description
Type
Supply
Digital Input
Digital Input
Digital Input
Digital Input
Digital Output
Analog Output
Type 2
Type 2
Type 2
Type 2
Type 4
Type 5
Equivalent Schematic
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3
AMIS−30521, NCV70521
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
V
BB
V
DD
T
ST
T
J
V
ESD
V
ESD
Parameter
Analog DC Supply Voltage (Note 1)
Logic Supply Voltage
Storage Temperature
Junction Temperature (Note 2)
Electrostatic Discharges on Component Level, All Pins (Note 3)
Electrostatic Discharges on Component Level, HiV Pins (Note 4)
Min
−0.3
−0.3
−55
−50
−2
−8
Max
+40
+7.0
+160
+175
+2
+8
Unit
V
V
°C
°C
kV
kV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. For limited time < 0.5s
2. Circuit functionality not guaranteed.
3. Human Body Model (100 pF via 1.5 kW, according to JEDEC EIA−JESD22−A114−B)
4. HiV = High Voltage Pins MOTxx, V
BB
, GND; Human Body Model (100 pF via 1.5 kW, according to JEDEC EIA−JESD22−A114−B)
Table 3. THERMAL RESISTANCE
Thermal Resistance
Junction−to−Ambient
Package
NQFP−32
Junction−to−Exposed Pad
0.95
1S0P Board
60
2S2P Board
30
Unit
K/W
EQUIVALENT SCHEMATICS
The following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified
representations of the circuits used.
4k
OUT
Rpd
IN
TYPE 1: CLR Input
TYPE 4: DO and ERR Open
Drain Outputs
R
out
SLA
IN
4k
TYPE 2: CLK, DI, CS, NXT, DIR Inputs
VDD
VBB
TYPE 5: SLA Analog Output
VDD
VBB
TYPE 3: V
DD
and V
BB
Power Supply Inputs
Figure 2. In− and Output Equivalent Diagrams
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AMIS−30521, NCV70521
PACKAGE THERMAL CHARACTERISTICS
The AMIS−30521/NCV70521 is available in an
NQFP−32 package. For cooling optimizations, the NQFP
has an exposed thermal pad which has to be soldered to the
PCB ground plane. The ground plane needs thermal vias to
conduct the heat to the bottom layer. Figure 3 gives an
example for good power distribution solutions.
For precise thermal cooling calculations the major
thermal resistances of the device are given. The thermal
media to which the power of the devices has to be given are:
•
Static environmental air (via the case)
•
PCB board copper area (via the exposed pad)
The thermal resistances are presented in Table 5: DC
Parameters.
The major thermal resistances of the device are the Rth
from the junction to the ambient (R
thja
) and the overall Rth
from the junction to exposed pad (R
thjp
). In Table 3 one can
find the values for the R
thja
simulated according to
JESD−51.
The R
thja
for 2S2P is simulated conform JEDEC JESD−51
as follows:
•
A 4−layer printed circuit board with inner power planes
and outer (top and bottom) signal layers is used
•
Board thickness is 1.46 mm (FR4 PCB material)
•
The 2 signal layers: 70
mm
thick copper with an area of
5500 mm
2
copper and 20% conductivity
•
The 2 power internal planes: 36
mm
thick copper with
an area of 5500 mm
2
copper and 90% conductivity
The R
thja
for 1S0P is simulated conform JEDEC JESD−51
as follows:
•
A 1−layer printed circuit board with only 1 layer
•
Board thickness is 1.46 mm (FR4 PCB material)
•
The layer has a thickness of 70
mm
copper with an area
of 5500 mm
2
copper and 20% conductivity
Figure 3. Example of NQFP−32 PCB Ground Plane Layout in Top View (Preferred Layout at Top and Bottom)
Recommended Operation Conditions
Operating ranges define the limits for functional
operation and parametric characteristics of the device. Note
that the functionality of the chip outside these operating
Table 4. OPERATING RANGES
Symbol
V
BB
V
DD
T
J
Analog DC supply
Logic supply voltage
Junction temperature
Parameter
5. No more than 100 cumulative hours in life time above T
tw
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NQFP−32
ELECTRICAL SPECIFICATION
ranges is not guaranteed. Operating outside the
recommended operating ranges for extended periods of time
may affect device reliability.
Min
+6
4.75
−40
Max
+30
5.25
+172 (Note 5)
Unit
V
V
°C
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