NB7V586M
1.8V Differential 2:1 Mux
Input to 1.2V/1.8V 1:6 CML
Clock/Data Fanout Buffer /
Translator
Description
Multi−Level Inputs w/ Internal Termination
The NB7V586M is a differential 1−to−6 CML Clock/Data
Distribution chip featuring a 2:1 Clock/Data input multiplexer with an
input select pin. The INx/INx inputs incorporate internal 50
W
termination resistors and will accept differential LVPECL, CML, or
LVDS logic levels (see Figure 12). The INx/INx inputs and core logic
are powered with a 1.8 V supply. The NB7V586M produces six
identical differential CML output copies of Clock or Data. The outputs
are configured as three banks of two differential pair. Each bank (or all
three banks) have the flexibility of being powered by any combination
of either a 1.8 V or 1.2 V supply.
The 16 mA differential CML output structure provides matching
internal 50
W
source terminations and 400 mV output swings when
externally terminated with a 50
W
resistor to V
CCO
x (see Figure 11).
The 1:6 fanout design was optimized for low output skew and
minimal jitter and is ideal for SONET, GigE, Fiber Channel,
Backplane and other Clock/Data distribution applications operating
up to 6 GHz or 10 Gb/s typical. The V
REFAC
reference outputs can be
used to rebias capacitor−coupled differential or single−ended input
signals.
The NB7V586M is offered in a low profile 5x5 mm 32−pin Pb−Free
QFN package. Application notes, models, and support documentation
are available at www.onsemi.com.
The NB7V586M is a member of the GigaComm™ family of high
performance clock products.
Features
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MARKING
DIAGRAM*
1
1
32
QFN32
MN SUFFIX
CASE 488AM
NB7V
586M
AWLYYWW
G
A
WL
YY
WW
G or
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
SIMPLIFIED LOGIC DIAGRAM
V
CC
Q0
Q0
V
CCO1
SEL
V
REFAC0
IN0
VT0
IN0
0
Q2
Q2
V
CCO2
IN1
VT1
IN1
V
REFAC1
V
CC
GND
1
Q3
Q3
Q1
Q1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Maximum Input Data Rate > 10 Gb/s Typical
Data Dependent Jitter < 10 ps
Maximum Input Clock Frequency > 6 GHz Typical
Random Clock Jitter < 0.8 ps RMS, Max
Low Skew 1:6 CML Outputs, 20 ps Max
2:1 Multi−Level Mux Inputs
175 ps Typical Propagation Delay
50 ps Typical Rise and Fall Times
Differential CML Outputs, 330 mV Peak−to−Peak, Typical
Operating Range: V
CC
= 1.71 V to 1.89 V
Operating Range: V
CCO
x = 1.14 V to 1.89 V
Internal 50
W
Input Termination Resistors
V
REFAC
Reference Output
QFN32 Package, 5 mm x 5 mm
−40°C
to +85°C Ambient Operating Temperature
These are Pb−Free Devices
Q4
Q4
V
CCO3
Q5
Q5
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
©
Semiconductor Components Industries, LLC, 2008
September, 2008
−
Rev. 0
1
Publication Order Number:
NB7V586M/D
NB7V586M
VCC01
Exposed Pad
(EP)
Table 1. INPUT SELECT FUNCTION TABLE
SEL*
0
CLK Input Selected
IN0
IN1
GND
VCC
SEL
Q1
27
Q0
32
IN0
VT0
VREFAC0
1
2
3
4
5
6
7
8
9
GND
31
30
29
28
Q0
26
Q1
25
24
23
22
21
GND
VCC02
Q2
Q2
Q3
Q3
VCC02
1
*Defaults HIGH when left open.
IN0
IN1
VT1
VREFAC1
IN1
NB7V586M
20
19
18
17
GND
10
NC
11
VCC03
12
Q5
13
Q5
14
Q4
15
Q4
16
VCC03
Figure 1. 32−Lead QFN Pinout
(Top View)
Table 2. PIN DESCRIPTION
Pin
1,4
5,8
2,6
31
10
30
25
18, 23
11, 16
29, 28
27, 26
22, 21
20, 19
15, 14
13, 12
9, 17,
24, 32
3
7
−
Name
IN0, IN0
IN1, IN1
VT0, VT1
SEL
NC
VCC
VCCO1
VCCO2
VCCO3
Q0, Q0
Q1, Q1
Q2, Q2
Q3, Q3
Q4, Q4
Q5, Q5
GND
VREFAC0
VREFAC1
EP
−
−
1.2 V or 1.8 V
CML Output
1.2 V or 1.8 V
CML Output
1.2 V or 1.8 V
CML Output
−
LVTTL/LVCMOS
Input
−
−
I/O
LVPECL, CML,
LVDS Input
Description
Non−inverted, Inverted, Differential Inputs
Internal 100
Ω
Center−tapped Termination Pin for IN0/IN0 and IN1/IN1
Input Select pin; LOW for IN0 Inputs, HIGH for IN1 Inputs; defaults HIGH when left open
No Connect
1.8 V Positive Supply Voltage for the Inputs and Core Logic.
1.2 V or 1.8 V Positive Supply Voltage for the Q0, Q0, Q1, Q1 CML Outputs
1.2 V or 1.8 V Positive Supply Voltage for the Q2, Q2, Q3, Q3 CML Outputs
1.2 V or 1.8 V Positive Supply Voltage for the Q4, Q4, Q5, Q5 CML Outputs
Non−inverted, Inverted Differential Outputs; powered by VCCO1 (Notes 1 and 2).
Non−inverted, Inverted Differential Outputs; powered by VCCO2 (Notes 1 and 2).
Non−inverted, Inverted Differential Outputs; powered by VCCO3 (Notes 1 and 2).
Negative Supply Voltage, connected to Ground
Output Voltage Reference for Capacitor−Coupled Inputs, only
The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is electrically connected to the die, and must be electric-
ally and thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and
if no signal is applied on INn/INn input, then, the device will be susceptible to self−oscillation. Qn/Qn outputs have internal 50
W
source
termination resistors.
2. All V
CC
, VCC0x and GND pins must be externally connected to a power supply for proper operation.
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NB7V586M
Table 3. ATTRIBUTES
Characteristics
ESD Protection
Input Pullup Resistor (R
PU
)
Moisture Sensitivity (Note 3)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
Human Body Model
Machine Model
Value
> 2 kV
> 200 V
75 kW
Level 1
UL 94 V−0 @ 0.125 in
308
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
CCOx
V
IO
V
INPP
I
IN
I
OUT
I
VFREFAC
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Positive Power Supply
Input/Output Voltage
Differential Input Voltage |IN
x
−
IN
x
|
Input Current Through R
T
(50
Ω
Resistor)
Output Current
V
REFAC
Sink/Source Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(Note 4)
Thermal Resistance (Junction−to−Case)
(Note 4)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
Standard Board
QFN−32
QFN−32
QFN−32
Continuous
Surge
Condition 1
GND = 0 V
GND = 0 V
GND = 0 V
−0.5
v
V
IO
v
V
CC
+ 0.5
Condition 2
Rating
3.0
3.0
−0.5
to V
CC
+ 0.5
1.89
$40
34
40
$1.5
−40
to +85
−65
to +150
31
27
12
265
Unit
V
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB7V586M
Table 5. DC CHARACTERISTICS
−
CML OUTPUT
V
CC
= 1.8 V
$5%,
V
CCO1
= 1.2 V
$5%
or 1.8 V
$5%,
V
CCO2
= 1.2 V
$5%
Symbol
Characteristic
Min
Typ
Max
Unit
or 1.8 V
$5%,
V
CCO3
= 1.2 V
$5%
or 1.8 V
$5%,
GND = 0 V, T
A
=
−40°C
to 85°C (Note 5)
POWER SUPPLY CURRENT
(Inputs and Outputs open)
I
CC
I
CCO
Power Supply Current for V
CC
Power Supply Current for VCCOx
(Inputs and Outputs Open)
(Inputs and Outputs Open)
75
95
125
105
mA
CML OUTPUTS
(Note 6)
V
OH
Output HIGH Voltage
V
CC
= 1.8 V, VCCOx = 1.8 V
V
CC
= 1.8 V, VCCOx = 1.2 V
V
CC
= 1.8 V, VCCOx = 1.8 V
V
CC
= 1.8 V, VCCOx = 1.2 V
V
CCOx
– 40
1760
1160
V
CCOx
– 500
1300
700
V
CCOx
– 20
1780
1180
V
CCOx
– 400
1400
800
V
CCOx
1800
1200
V
CCOx
– 275
1525
925
mV
V
OL
Output LOW Voltage
mV
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED
(Note 7) (Figure 6)
V
th
V
IH
V
IL
V
ISE
V
REFAC
V
REFAC
Output Reference Voltage @ 100
mA
for Capacitor
−
Coupled
Inputs, Only
V
CC
−
550
V
CC
−
450
V
CC
−
300
mV
Input Threshold Reference Voltage Range (Note 8)
Single−Ended Input HIGH Voltage
Single−Ended Input LOW Voltage
Single−Ended Input Voltage (V
IH
−
V
IL
)
1050
V
th
+ 100
GND
200
V
CC
−
100
V
CC
V
th
−
100
1200
mV
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Note 9) (Figures 4 and 7)
V
IHD
V
ILD
V
ID
V
CMR
I
IH
I
IL
V
IH
V
IL
I
IH
I
IL
R
TIN
R
TOUT
Differential Input HIGH Voltage (IN, IN)
Differential Input LOW Voltage (IN, IN)
Differential Input Voltage (IN, IN) (V
IHD
−
V
ILD
)
Input Common Mode Range (Differential Configuration, Note 10)
(Figure 9)
Input HIGH Current IN/IN (VTO / VT1 Open)
Input LOW Current IN/IN (VTO / VT1 Open)
1100
GND
100
1050
−150
−150
V
CC
V
CC
−
100
1200
V
CC
−
50
150
150
mV
mV
mV
mV
mA
mA
CONTROL INPUT
(SEL Pin)
Input HIGH Voltage for Control Pin
Input LOW Voltage for Control Pin
Input HIGH Current
Input LOW Current
V
CC
x 0.65
GND
−150
−150
20
5
V
CC
V
CC
x 0.35
+150
+150
mV
mV
mA
mA
TERMINATION RESISTORS
Internal Input Termination Resistor (Measured from INx to VTx)
Internal Output Termination Resistor
45
45
50
50
55
55
W
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input parameters vary 1:1 with V
CC
. and output parameters vary 1:1 with V
CCOx
.
6. CML outputs (Qn/Qn) have internal 50
W
source termination resistors and must be externally terminated with 50
W
to V
CCOx
for proper
operation.
7. V
th
, V
IH,
V
IL
and V
ISE
parameters must be complied with simultaneously.
8. V
th
is applied to the complementary input when operating in single−ended mode.
9. V
IHD
, V
ILD
, V
ID
and V
CMR
parameters must be complied with simultaneously.
10. V
CMR
min varies 1:1 with GND, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential
input signal.
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NB7V586M
Table 6. AC CHARACTERISTICS
V
CC
= 1.8 V
$5%,
V
CCO1
= 1.2 V
$5%
or 1.8 V
$5%,
V
CCO2
= 1.2 V
$5%
or 1.8 V
$5%,
Symbol
f
MAX
f
DATAMAX
V
OUTPP
t
PLH
, t
PHL
t
PLH
TC
t
SKEW
t
DC
t
JITTER
V
INPP
t
r
, t
f
Characteristic
Maximum Input Clock Frequency, V
OUTPP
w
200 mV
Maximum Operating Input Data Rate (PRBS23)
Output Voltage Amplitude (See Figures 4, Note 15)
Propagation Delay to Output Differential @ 1 GHz,
Measured at Differential Crosspoint
Propagation Delay Temperature Coefficient
Output
−
Output Skew (Within Device) (Note 12)
Device
−
Device Skew (t
pd
Max
−
t
pdmin
)
Output Clock Duty Cycle (Reference Duty Cycle = 50%) f
in
v
4.0 GHz
Output Random Jitter (RJ) (Note 13)
Deterministic Jitter (DJ) (Note 14)
Input Voltage Swing (Differential Configuration) (Note 15)
Output Rise/Fall Times @ 1 GHz (20%
−
80%)
Q
n
, Q
n
f
in
v
4.0 GHz
10 Gbps
100
50
45
50
0.2
f
in
v
4.0 GHz
IN
x
/IN
x
to Q
n
/Q
n
SEL to Q
n
Min
4.0
10
200
125
125
330
175
100
30
50
55
0.8
10
1200
65
250
300
Typ
6.0
Max
Unit
GHz
Gbps
mV
ps
fs/°C
ps
%
ps rms
ps pk−pk
mV
ps
V
CCO3
= 1.2 V
$5%
or 1.8 V
$5%,
GND = 0 V, T
A
=
−40°C
to 85°C (Note 11)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 400 mV source, 50% duty cycle clock source. All outputs must be loaded with external 50
W
to V
CCOx
. Input edge rates
40 ps (20%
−
80%).
12. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from cross−point of the inputs to the crosspoint of the outputs.
13. Additive RMS jitter with 50% duty cycle clock signal.
14. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23.
15. Input and output voltage swing is a single−ended measurement operating in differential mode.
400
OUTPUT VOLTAGE AMPLITUDE
(mV)
350
300
250
IN
x
200
150
100
V
Tx
50
W
IN
x
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
f
out
, CLOCK OUTPUT FREQUENCY (GHz)
50
W
V
CC
Figure 2. Output Voltage Amplitude (V
OUTPP
) vs. Input
Frequency (f
in
) at Ambient Temperature (Typical)
Figure 3. Input Structure
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