NB4N1158
Link Replicator for Fibre
Channel, Gigabit Ethernet,
HDTV and SATA
Up to 1.5 Gb/s
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Description
The NB4N1158 is a high performance 3.3 V Serial Link Replicator
which provides the function of serial loop replication and serial
loopback control commonly required in Fibre Channel, GbE, HDTV
and SATA applications. Other popular applications include Host Bus
Adaptors for routing between internal and external connectors, and
hot-pluggable links between redundant switch fabric cards.
IN is sent to both OUT0 and OUT1; each output is enabled by OE0
and OE1 when HIGH. OUT0 can select either IN or IN1 via the
MUX0 pin. Likewise, OUT1 can select between IN or IN0 via the
MUX1 pin. Out can select between IN0 and IN1.
In Link Replicator applications, such as the Line Card to Switch
Card links, IN is transmitted to both OUT0 and OUT1 which either
IN0 or IN1 is selected at OUT. In Host Adapter applications, IN goes
to OUT0 (an internal connector) which returns data on IN0. IN0 is
looped to OUT1 (an external connector) which returns data on IN1 and
then back to the SerDes on OUT.
The NB4N1158 is packaged in a 4.7 mm x 9.7 mm TSSOP-28.
Features
28 Lead TSSOP
DT SUFFIX
CASE 948A
MARKING DIAGRAM*
NB4N
1158
ALYW
•
Replicates Fibre Channel, Gigabit Ethernet, HDTV, and
•
•
•
•
•
•
•
•
Serial ATA (SATA) Links
T11 Fibre Channel Complaint at 1.0625 Gb/s
Differential LVPECL Outputs, External Load/Termination
Resistors Required
IEEE802.3z Gigabit Ethernet Compliant at 1.25 Gb/s
SMPTE-292M Compliant at 1.485 Gb/s
330 mW Maximum Power Dissipation
Operating Range: V
CC
= 3.135 V to 3.465 V
28-pin, 4.4 mm x 9.7 mm TSSOP Package
These are Pb-Free Devices
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G or
G
= Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
NB4N1158
LOOP0
TX
RX
LOOP1
Figure 1. Simplified Application
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
1
December, 2007 - Rev. 0
Publication Order Number:
NB4N1158/D
NB4N1158
TYPICAL APPLICATIONS CIRCUIT
VDDP0
OE0
IN0+
IN0-
MUX
GND
IN+
IN-
GND
OE1
VDD
VDDP
OUT+
OUT-
VDDP
GND
1
2
3
4
5
6
7
NB4N1158
8
9
10
11
12
13
14
28 OUT0+
27 OUT0-
26 VDDP0
25 GND
24 IN0+
23 IN0-
22 VDDP1
21 OUT1+
20 OUT1-
19 VDDP1
18 IN1+
17 IN1-
16 MUX0
15 MUX1
IN+
IN-
OE0
0
OUT0+
OUT0-
1
OUT+
OUT-
0
MUX0
1
IN1+
IN1-
0
OE1
OUT1+
OUT1-
1
MUX1
MUX
Figure 2. Simplified Block Diagram
Table 1. OE, OUTPUT ENABLE FUNCTION
OEx*
1
0
*Defaults to HIGH when left open
Function
Figure 3. Pin Diagram for TSSOP-28
Outputs Enabled
Outputs Disabled OUTn+ = H, OUTn- = H
Table 2. PIN DESCRIPTION
Pin
5, 6
24, 23
18, 17
11, 12
28, 27
21, 20
2
8
3
15
16
9
10, 13
1, 26
19, 22
4, 7, 14, 25
Name
IN+, IN-
IN0+, IN0-
IN1+, IN1-
OUT+, OUT-
OUT0+, OUT0-
OUT1+, OUT1-
OE0
OE1
MUX
MUX1
MUX0
VDD
VDDP
VDDP0
VDDP1
GND
I/O
LVPECL Input
LVPECL Input
LVPECL Input
LVPECL Output
LVPECL Output
LVPECL Output
LVTTL Input
LVTTL Input
LVTTL Input
LVTTL Input
LVTTL Input
Power Supply
Power Supply
Description
Non-inverted, Inverted, Differential Data Inputs internally biased to
Approximately 1.2 V.
Non-inverted, Inverted Differential Outputs. Typically terminated with 50
W
resistor to V
CC
- 2.0 V.
OE0/OE1 enables OUT0/OUT1 when HIGH. When LOW, OUTx are
powered down and both OUT+ and OUT- float HIGH.
Selects Source for OUT, Selects Either IN0 (LOW) or IN1 (HIGH); defaults
HIGH when left open.
Selects Source for OUT1. Selects Either IN (HIGH) or IN0 (LOW); defaults
HIGH when left open.
Selects Source for OUT0. Selects either IN (LOW) or IN1 (HIGH); defaults
HIGH when left open.
3.3 V Positive Supply Voltage for Digital Logic.
3.3 V supply for LVPECL output drivers. VDDP is for OUT, VDDP0 is for
OUT0, and VDDP1 is for OUT1.
Negative Supply Voltage, Connected to Ground
Power Supply
All VDD, VDDPx and GND Pins must be externally connected to appropriate power supply to guarantee proper operation.
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NB4N1158
Table 3. ATTRIBUTES
Characteristics
Internal Input Pullup Resistor
ESD Protection
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
Human Body Model
Machine Model
Value
96 kW
> 1 kV
> 100 V
Level 3
UL 94 V-0 @ 0.125 in
268 Devices
Table 4. MAXIMUM RATINGS
Symbol
V
DD
V
INP
V
INT
I
OUT
T
C
TA
T
stg
q
JA
q
JC
T
sol
Positive Power Supply
Input Voltage, PECL
Input Voltage, TTL
Output HIGH current, PECL
Case temperature under bias
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction-to-Ambient)
Thermal Resistance (Junction-to-Case)
Wave Solder
Pb-Free
0 lfpm
500 lfpm
(Note 2)
Parameter
Condition 1
GND = 0 V
GND = 0 V
GND = 0 V
Min
0.5
-0.5
-0.5
-50
-55
-40
-65
TSSOP-28
TSSOP-28
Max
4.0
V
DD
+ 0.5
V
DD
+ 0.5
+50
+125
+85
+150
76
60
25
265
Unit
V
V
V
mA
°C
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board - 2S2P (2 signal, 2 power).
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NB4N1158
Table 5. DC CHARACTERISTICS
V
DD
= 3.30 V
$5%,
GND = 0 V; T
A
= -40°C to +85°C (Note 3)
Symbol
V
DD
I
DD
P
D
DV
IN
DV
OUT50
Characteristic
Power Supply Voltage, 3.30 V
$5%
Power Supply Current (Outputs open)
Power Dissipation; Outputs Open; V
DD
= V
DDmax
Receiver Differential Voltage Amplitude; (IN, IN0, IN1), AC-Coupled,
Internally Biased to 1.2 V; Differential Measurement - (V
INn+
- V
INn-
)
Output Differential Voltage Swing, peak-peak; (OUT, OUT0, OUT1)
Outputs loaded / terminated with 50
W
to V
DD
– 2.0 V
Differential Measurement - (V
OUTn+
- V
OUTn-
)
Output Differential Voltage Swing, peak-peak; (OUT, OUT0, OUT1)
Outputs loaded / terminated with 75
W
to V
DD
– 2.0 V
Differential Measurement - (V
OUTn+
- V
OUTn-
)
300
1000
1600
Min
3.14
57
Typ
Max
3.47
75
330
2600
mV
2200
mV
1200
1650
2200
Unit
V
mA
mW
mV
DV
OUT75
LVCMOS/LVTTL INPUTS
V
IH
V
IL
I
IH
I
IL
Input HIGH Voltage, TTL
Input LOW Voltage, TTL
Input HIGH Current, TTL; V
IN
= 2.4 V
Input LOW Current, TTL; V
IN
= 0.5 V
-100
2.0
0
V
DD
+ 0.5
0.8
100
V
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. LVPECL outputs loaded with external 50
W
termination resistors to V
TT
= V
DD
- 2.0 V for proper operation (see Figure 6).
Table 6. AC CHARACTERISTICS
V
DD
= 3.3 V
$5%,
GND = 0 V -40°C to +85°C
Symbol
f
IN / OUT
tr/tf
t
PD
T
DJ
Characteristic
Input / Output Frequency Range
Output rise and Fall Times (Note 4)
Propagation Delay, IN to OUT
Deterministic Jitter Added to Serial Input Up to 1.5 Gb/s;
K28.5$ Pattern
Min
1.0
110
0.375
Typ
Max
1.5
150
4.0
40
Unit
Gb/s
ps
ns
ps pk-pk
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measured 20% to 80%
IN+/-
IN0+/-
IN1+/-
OUT+/-
OUT0+/-
OUT1+/-
t
pd
t
pd
t
J
Figure 4. Timing Waveforms
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NB4N1158
0.01mF
TX+
R
0.01mF
TX-
R
SerDes
0.01mF
RX+
RT
RX-
R
R
0.01mF
O-
I1-
O+
I1+
NB4N1158
RT
I-
O1-
I+
O1+
0.01mF
I1+
R
0.01mF
R
NB4N1158
0.01mF
O1+
R
RT
0.01mF
O1-
R
I-
I+
RT
I1-
O-
O+
0.01mF
RX+
R
0.01mF
R
SerDes
0.01mF
TX+
RT
R
0.01mF
TX-
R
RT
RX-
“R” is 150
W
for both 100
W
differential or 150
W
differential traces.
“RT” matches the differential impedance of the link.
Figure 5. NB4N1158 Application Interface Example
IN+/IN- Input Functionality
OEx Output Enable
The differential inputs are internally biased to
Y1.2
V. In
a typical application, the differential inputs are
capacitor-coupled and will swing symmetrically above and
below 1.2 V, preserving a 50% duty cycle to the outputs.
With this technique, the NB4N1158 will accept any
differential input allowing for LVPECL, CML, LVDS, and
HSTL input levels.
OUT+ / OUT- Outputs
The NB4N1158 incorporates output enable pins, OE0 and
OE1, that work by powering down the output buffer and
associated driving circuitry. Using this approach results in
both differential outputs going HIGH, and a reduction in I
DD
current of approx. 29 mA for each disabled output pair.
When OEx is LOW, outputs are disabled, OUTx+ and
OUTx- are set HIGH.
Power Supply Bypass information
The differential output buffers of the NB4N1158 utilize
standard Positive Emitter Coupled Logic (PECL)
architecture for OUT+ and OUT-. The outputs are designed
to drive differential transmission lines with nominally 50
W
or 75
W
characteristic
impedance.
External
DC load/termination with a 50
W
resistor to V
TT
= V
DD
-
2.0 V is required. See Figure 6 for output termination
scheme.
A clean power supply will optimize the performance of
the device. The NB4N1158 provides separate power supply
pins for the digital circuitry (V
DD
) and LVPECL outputs
(VDDPn). Placing a bypass capacitor of 0.01
mF
to 0.1
mF
on each VDD pin will help ensure a noise free V
DD
power
supply. The purpose of this design technique is to try and
isolate the high switching noise of the digital outputs from
the relatively sensitive digital core logic.
Q
Driver
Device
Q
Z
o
= 50
W
D
Receiver
Device
Z
o
= 50
W
50
W
50
W
D
V
TT
V
TT
= V
CC
- 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D - Termination of ECL Logic Devices.)
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