MDT10C55B
1. General Description
This ROM-Based 8-bit micro-controller uses a fully
static CMOS technology process to achieve higher
speed
and
smaller
size
with
the
low
power
Power-on Reset
Power edge-detector Reset
Sleep Mode for power saving
5 types of oscillator can be selected by
programming option:
INTRC－Internal 4 MHz RC oscillator
RC－Low cost RC oscillator
LFXT－Low frequency crystal oscillator
XTAL－Standard crystal oscillator
consump-tion and high noise immunity. On chip
memory inclu-des 1K words of ROM, and 72 bytes of
static RAM.
2. Features
The followings are some of the features on the
hardware and software :
Fully CMOS static design
8-bit data bus
On chip ROM size : 1K words
Internal RAM size : 72 bytes
36 single word instructions
14-bit instructions
2-level stacks
Operating voltage : 2.5 V ~ 5.5 V
Operating frequency : 0 ~ 20 MHz
The most fast execution time is 200 ns under
20 MHz in all single cycle instructions except
the branch instruction
Addressing modes include direct, indirect and
relative addressing modes
HFXT－High frequency crystal oscillator
3 oscillator start-up time can be selected by
programming option:
20 ms, 40 ms, 80 ms
8-bit real time clock/counter(RTCC) with 8-bit
programmable prescaler
On-chip RC oscillator based Watchdog
Timer(WDT)
Wake-up from sleep on pin change
3. Applications
The application areas of this MDT10C55B range
from appliance motor control and high speed
automotive to low power remote
transmitters/receivers, small instruments, chargers,
toy, automobile and PC pe-ripheral … etc.
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 1
2006/12
Ver. 1.0
MDT10C55B
4. Pin Assignment
MDT10C55B1P/MDT10C55B1S
MDT10C55B3P/MDT10C55B3S
VDD 1
PB5
PB4
PB3
PC5/RTCC
PC4
PC3
2
3
4
5
6
7
14 VSS
13
12
11
10
9
8
PB0
PB1
PB2
PC0
PC1
PC2
VDD
PB5
PB4
/MCLR
PC5/RTCC
PC4
PC3
VDD
OSC1
OSC2/PB4
/MCLR
PC5/RTCC
PC4
PC3
1
2
3
4
5
6
7
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
13
12
11
10
9
8
VSS
PB0
PB1
PB2
PC0
PC1
PC2
VSS
PB0
PB1
PB2
PC0
PC1
PC2
MDT10C55B2P/MDT10C55B2S
MDT10C55B4P/MDT10C55B4S
VDD 1
OSC1
OSC2/PB4
PB3
PC5/RTCC
PC4
PC3
2
3
4
5
6
7
14 VSS
12
12
11
10
9
8
PB0
PB1
PB2
PC0
PC1
PC2
5. Pin Function Description
Pin Name
PB5~0
PC4~0
PC5/RTCC
/MCLR
OSC1
OSC2
V
dd
V
ss
I/O
I/O
I/O
I/O
I
I
O
Function Description
Port B, TTL input level, PB3 input only.
Port C, TTL input level.
Real Time Clock/Counter, Schmitt Trigger input levels.
Master Clear, Schmitt Trigger input levels.
Oscillator Input
Oscillator Output
Power supply
Ground
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 2
2006/12
Ver. 1.0
MDT10C55B
6. Memory Map
(A) Register Map
Address
00
01
02
03
04
06
07
08~1F
30~3F
50~5F
70~7F
(1) IAR (Indirect Address Register) : R0
(2) RTCC (Real Time Counter/Counter register) : R1
(3) PC (Program Counter) : R2
Write PC, CALL --- always 0
JUMP --- from instruction word
RTWI, RET --- from STACK
General purpose registers
Description
Indirect Addressing Register
RTCC
PC
STATUS
MSR
Port B
Port C
A9
A8
Write PC, JUMP, CALL --- from STATUS b5
RTWI, RET --- from STACK
A7~A0
Write PC --- from ALU
JUMP, CALL --- from instruction word
RTWI, RET --- from STACK
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 3
2006/12
Ver. 1.0
MDT10C55B
(4) STATUS (Status register) : R3
Bit
0
1
2
3
4
5
6
7
Symbol
C
HC
Z
PF
TF
PAGE
——
PCWUF
Carry bit
Half Carry bit
Zero bit
Power down bit
WDT Timer overflow Flag bit
ROM page select bit
Unimplemented
Pin change wake up from sleep
Function
(5) MSR (Memory Bank Select Register) : R4
b7
b6
b5
b4
b3
b2
b1
b0
Read only “1”
BANK Select
Indirect Addressing Mode
(6) PORT B : R6
PB5~PB0, I/O register, PB3 input only.
(7) PORT C: R7
PC5~PC0, I/O register.
(8) TMR (Time Mode Register)
Bit
Symbol
Function
Prescaler Value
RTCC rate
0 0 0
1:2
0 0 1
1:4
0 1 0
1:8
0 1 1
1 : 16
1 0 0
1 : 32
1 0 1
1 : 64
1 1 0
1 : 128
1 1 1
1 : 256
Prescaler assignment bit :
0: RTCC
1: Watchdog Timer
RTCC signal Edge :
0: Increment on low-to-high transition on RTCC pin
1: Increment on high-to-low transition on RTCC pin
RTCC signal set :
0: Internal instruction cycle clock
1: Transition on RTCC pin
PortB pull-high :(RB0,RB1,RB3,RB4)
0: Enable
1: Disable
WDT rate
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
2—0
PS2—0
3
PSC
4
TCE
5
TCS
6
PBPHB
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 4
2006/12
Ver. 1.0
MDT10C55B
Bit
7
Symbol
PBWUB
Function
PortB wake-up : (RB0,RB1,RB3,RB4)
0: Enable
1: Disable
(9) CPIO B, CPIO C (Control Port I/O Mode Register)
The CPIO register is “write-only”
＝“0”,
I/O pin in output mode;
＝“1”,
I/O pin in input mode.
(B) Program Memory
Address
000-3FF
000
Program memory
The starting address of power on, external reset or WDT time-out reset.
Description
8. Reset Condition for all Registers
Register
CPIO B
CPIO C
TMR
IAR
RTCC
PC
STATUS
MSR
PORT B
PORT C
Address
－－
－－
－－
00h
01h
02h
03h
04h
06h
07h
Power-On Reset
--11 1111
--11 1111
1111 1111
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
110x xxxx
--xx xxxx
--xx xxxx
/MCLR Reset
--111 1111
--11 1111
1111 1111
uuuu uuuu
uuuu uuuu
0000 0000
#00# #uuu
11uu uuuu
--uu uuuu
--uu uuuu
WDT Reset
--11 1111
--11 1111
--11 1111
uuuu uuuu
uuuu uuuu
0000 0000
#00# #uuu
11uu uuuu
--uu uuuu
--uu uuuu
Note : u＝unchanged, x＝unknown, -
＝unimplemented,
read as “0”
#＝value depends on the condition of the following table
Condition
/MCLR reset (not during SLEEP)
/MCLR reset during SLEEP
WDT reset (not during SLEEP)
WDT reset during SLEEP
Wake-up from SLEEP on pin change
Status: bit 7
0
0
0
0
1
Status: bit 4
u
1
0
0
1
Status: bit 3
u
0
1
0
0
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 5
2006/12
Ver. 1.0
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