Datasheet> 器件分类 > 存储> 存储> CYDD04S18V18-167BBI

文档预览

CYDD04S18V18-167BBI: 产品描述Dual-Port SRAM, 128KX36, 9ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, MO-192, FBGA-256; 产品类别存储存储; 文件大小953KB，共48页; 制造商Cypress(赛普拉斯)

下载文档详细参数全文预览

CYDD04S18V18-167BBI概述

Dual-Port SRAM, 128KX36, 9ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, MO-192, FBGA-256

CYDD04S18V18-167BBI规格参数

参数名称	属性值
是否无铅	含铅
是否Rohs认证	不符合
零件包装代码	BGA
包装说明	17 X 17 MM, 1 MM PITCH, MO-192, FBGA-256
针数	256
Reach Compliance Code	compliant
ECCN代码	3A991.B.2.A
最长访问时间	9 ns
其他特性	PIPELINED OR FLOW-THROUGH ARCHITECTURE, IT CAN ALSO OPERATE AT 1.8V
最大时钟频率 (fCLK)	167 MHz
I/O 类型	COMMON
JESD-30 代码	S-PBGA-B256
JESD-609代码	e0
长度	17 mm
内存密度	4718592 bit
内存集成电路类型	DUAL-PORT SRAM
内存宽度	36
湿度敏感等级	3
功能数量	1
端口数量	2
端子数量	256
字数	131072 words
字数代码	128000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	128KX36
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	LBGA
封装等效代码	BGA256,16X16,40
封装形状	SQUARE
封装形式	GRID ARRAY, LOW PROFILE
并行/串行	PARALLEL
峰值回流温度（摄氏度）	225
电源	1.5/1.8 V
认证状态	Not Qualified
座面最大高度	1.7 mm
最大待机电流	0.17 A
最小待机电流	1.5 V
最大压摆率	0.53 mA
最大供电电压 (Vsup)	1.58 V
最小供电电压 (Vsup)	1.42 V
标称供电电压 (Vsup)	1.5 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	Tin/Lead (Sn/Pb)
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	30
宽度	17 mm
Base Number Matches	1

文档预览

下载PDF文档

全文
预览

PRELIMINARY

FullFlex™ Synchronous

DDR Dual-Port SRAM

Features

• True dual-ported memory allows simultaneous access

to the shared array from each port

• Synchronous pipelined operation with selectable

Double Data Rate (DDR) or Single Data Rate (SDR)

operation on each port

— DDR SRAM interface (data transferred at 400 Mbps)

@ 200 MHz

— SDR interface at 250 MHz

— Up to 36-Gb/s bandwidth (250 MHz * 72 bit * 2 ports)

• Selectable pipeline or flow-through mode

• Selectable 1.5V or 1.8V core power supply

• Commercial and Industrial temperature ranges

• IEEE 1149.1 JTAG boundary scan

• Available in 484-ball PBGA Packages and 256-ball

FBGA Packages

• FullFlex72 family

— 36 Mbit: 512K x 72 (CYDD36S72V18)

— 18 Mbit: 256K x 72 (CYDD18S72V18)

— 9 Mbit: 128K x 72 (CYDD09S72V18)

— 4 Mbit: 64K x 72 (CYDD04S72V18)

• FullFlex36 family

— 36 Mbit: 512K x 72 (CYDD36S36V18)

— 18 Mbit: 256K x 72 (CYDD18S36V18)

— 9 Mbit: 128K x 72 (CYDD09S36V18)

— 4 Mbit: 64K x 72 (CYDD04S36V18)

• FullFlex18 family

— 36 Mbit: 1M x 36 (CYDD36S18V18)

— 18 Mbit: 512K x 36 (CYDD18S18V18)

— 9 Mbit: 256K x 36 (CYDD09S18V18)

— 4 Mbit: 128K x 36 (CYDD04S18V18)

• Built-in deterministic access control to manage

address collisions

— Deterministic flag output upon collision detection

— Collision detection on back-to-back clock cycles

— First Busy Address readback

• Advanced features for improved high-speed data

transfer and flexibility

— Variable impedance Matching (VIM)

— Echo clocks

— Selectable LVTTL (3.3V), Extended HSTL

(1.4V–1.9V), 1.8V LVCMOS, or 2.5V LVCMOS I/O on

each port

— Burst counters for sequential memory access

— Mailbox with interrupt flags for message passing

— Dual Chip Enables for easy depth expansion

Functional Description

The FullFlex Dual-Port SRAM families consist of 4-Mbit,

9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual-port static

RAMs that are high-speed, low-power 1.8V/1.5V CMOS. Two

ports are provided, allowing the array to be accessed simulta-

neously. Simultaneous access to a location triggers determin-

istic access control. For FullFlex72, these ports can operate

independently in DDR mode with 36-bit bus widths or in SDR

mode with 72-bit bus widths. For FullFlex36 and FullFlex18,

the ports operate in DDR mode only. Each port can be

independently configured for two pipeline stages for SDR

mode or 2.5 stages in DDR mode. Each port can also be

configured to operate in pipeline or flow-through mode in SDR

mode.

Advanced features include built-in deterministic access

control to manage address collisions during simultaneous

access to the same memory location, variable impedance

Matching (VIM) to improve data transmission by matching the

output driver impedance to the line impedance, and echo

clocks to improve data transfer.

To reduce the static power consumption, chip enables can be

used to power down the internal circuitry. The number of

cycles of latency before a change in CE0 or CE1 will enable

or disable the databus matches the number of cycles of read

latency selected for the device. In order for a valid write or read

to occur, both chip enable inputs on a port must be active.

Each port contains an optional burst counter on the input

address register. After externally loading the counter with the

initial address, the counter will increment the address inter-

nally.

Additional features of this device include a mask register and

a mirror register to control counter increments and

wrap-around, counter-interrupt (CNTINT) flags to notify that

the counter will reach the maximum value on the next clock

cycle, readback of the burst-counter internal address, mask

retransmit functionality, mailbox interrupt flags for message

passing, JTAG for boundary scan, and asynchronous Master

Reset (MRST). The logic block diagram in

Figure 1

displays

these features.

The FullFlex72 DDR family of devices is offered in a 484-ball

plastic BGA package. The FullFlex36 and FullFlex18 DDR

only families of devices are offered in a 256-ball fine pitch BGA

package.

Cypress Semiconductor Corporation

Document #: 38-06072 Rev. *E

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised October 11, 2005

CYDD04S18V18-167BBI

CYDD04S18V18-167BBI概述

CYDD04S18V18-167BBI规格参数

文档预览

推荐资源