• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Supports 3.3V I/O level
• Offered in JEDEC-standard 100-pin TQFP package
• “ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1344F is a 65,536 x 36 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
7.5 ns (117-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
[A:D]
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1344F allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1344F operates from a +3.3V core power supply
while all outputs may operate with a +3.3V supply. All inputs
and outputs are JEDEC-standard JESD8-5-compatible.
Logic Block Diagram
A0, A1, A
ADDRESS
REGISTER
A
[1:0]
MODE
ADV
CLK
BURST Q1
COUNTER
AND LOGIC
Q0
CLR
ADSC
ADSP
DQ
D
,
DQP
D
BW
D
BYTE
WRITE REGISTER
DQ
C
,
DQP
C
BYTE
WRITE REGISTER
DQ
B
,
DQP
B
BYTE
WRITE REGISTER
DQ
A
,
DQP
A
BW
A
BWE
GW
CE1
CE2
CE3
OE
DQ
A
,
DQP
A
BYTE
WRITE REGISTER
BYTE
WRITE REGISTER
DQ
D
,
DQP
D
BYTE
WRITE REGISTER
DQ
C
,
DQP
C
BYTE
WRITE REGISTER
DQ
B
,
DQP
B
BW
B
BYTE
WRITE REGISTER
BW
C
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQP
A
DQP
B
DQP
C
DQP
D
ENABLE
REGISTER
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05432 Rev. *A
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised April 9, 2004
CY7C1344F
Selection Guide
117 MHz
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
7.5
220
40
100 MHz
8.0
205
40
Unit
ns
mA
mA
Shaded area contains advance information. Please contact your local Cypress sales representative for availability of this part.
Pin Configurations
100-Pin TQFP
BW
D
BW
C
BW
B
BW
A
CE
3
CE
1
V
DD
V
SS
OE
ADSC
ADSP
ADV
86
85
84
83
CE
2
CLK
GW
BWE
A
A
82
A
99
98
97
96
95
94
93
92
91
90
89
88
87
DQP
C
DQ
C
DQ
C
V
DDQ
V
SSQ
DQ
C
DQ
C
BYTE C
DQ
C
DQ
C
V
SSQ
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SSQ
DQ
D
DQ
D
DQ
D
DQ
D
V
SSQ
V
DDQ
DQ
D
DQ
D
DQP
D
BYTE D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
100
81
A
CY7C1344F
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
43
44
45
46
47
48
49
50
DQP
B
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
DQP
A
BYTE B
BYTE A
38
39
40
V
SS
41
V
DD
NC
NC
A
A
NC
NC
A
1
A
0
42
MODE
A
Document #: 38-05432 Rev. *A
NC
A
A
A
A
A
A
A
Page 2 of 15
CY7C1344F
Pin Definitions
Name
A0, A1, A
TQFP
37,36,32,
33,34,35,
44,45,46,
47,48,49,
81,82,
99,100
93,94,
95,96
88
I/O
Description
Input-
Address Inputs used to select one of the 64K address locations.
Sampled at the
Synchronous rising edge of the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are
sampled active. A
[1:0]
feed the 2-bit counter.
BW
A
, BW
B
BW
C
, BW
D
GW
Input-
Byte Write Select Inputs, active LOW.
Qualified with BWE to conduct Byte Writes
Synchronous to the SRAM. Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW.
When asserted LOW on the rising edge of
Synchronous CLK, a global Write is conducted (ALL bytes are written, regardless of the values on
BW
[A:D]
and BWE).
Input-
Byte Write Enable Input, active LOW.
Sampled on the rising edge of CLK. This
Synchronous signal must be asserted LOW to conduct a Byte Write.
Input-Clock
Clock Input.
Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
BWE
CLK
CE
1
87
89
98
Input-
Chip Enable 1 Input, active LOW.
Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH.
Input-
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE
1
and CE
3
to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW.
Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE and CE to select/deselect the device.
1
2
Input-
Output Enable, asynchronous input, active LOW.
Controls the direction of the I/O
Asynchronous pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins
are three-stated, and act as input data pins. OE is masked during the first clock of a
read cycle when emerging from a deselected state.
Input-
Advance Input signal, sampled on the rising edge of CLK.
When asserted, it
Synchronous automatically increments the address in a burst cycle.
Input-
Address Strobe from Processor, sampled on the rising edge of CLK, active
Synchronous
LOW.
When asserted LOW, addresses presented to the device are captured in the
address registers. A
[1:0]
are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE
1
is
deasserted HIGH
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active
Synchronous
LOW.
When asserted LOW, addresses presented to the device are captured in the
address registers. A
[1:0]
are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
Input-
ZZ “sleep” Input, active HIGH.
When asserted HIGH places the device in a
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
CE
2
CE
3
OE
97
92
86
ADV
ADSP
83
84
ADSC
85
ZZ
64
DQs
52,53,56,
I/O-
Bidirectional Data I/O lines.
As inputs, they feed into an on-chip data register that
DQP
A,
DQP
B
57,58,59, Synchronous is triggered by the rising edge of CLK. As outputs, they deliver the data contained in
DQP
C,
DQP
D
62,63,68,
the memory location specified by the addresses presented during the previous clock
69,72,73,
rise of the Read cycle. The direction of the pins is controlled by OE. When OE is
74,75,78,
asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP
[A:D]
are
79,2,3,6,
placed in a three-state condition.
7,8,9,12,
13,18,19,
22,23,24,
25,28,29,
51,80,1,30
V
DD
15,41,
65, 91
Power
Supply
Power supply inputs to the core of the device.
Document #: 38-05432 Rev. *A
Page 3 of 15
CY7C1344F
Pin Definitions
(continued)
Name
V
SS
V
DDQ
TQFP
17,40,
67,90
4,11,20,
27,54,61,
70,77
,
5,10,21,55
,60,71,76
31
I/O
Ground
I/O Power
Supply
I/O Ground
Input-
Static
Description
Ground for the core of the device.
Power supply for the I/O circuitry.
V
SSQ
MODE
Ground for the I/O circuitry.
Selects Burst Order.
When tied to GND selects linear burst sequence. When tied to
V
DD
or left floating selects interleaved burst sequence. This is a strap pin and should
remain static during device operation. Mode pin has an internal pull-up.
No Connects.
Not Internally connected to the die.
NC
14,16,38,
39,42,43,
50,66,
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t
CDV
) is 7.5 ns (117-MHz device).
The CY7C1344F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All Writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE
1
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
1
, CE
2
, and CE
3
are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to t
CDV
after clock
rise. ADSP is ignored if CE
1
is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
1
, CE
2
, CE
3
are all asserted
active, and (2) ADSP is asserted LOW. The addresses
Document #: 38-05432 Rev. *A
presented are loaded into the address register and the burst
inputs (GW, BWE, and BW[A:D]) are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
Write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte Writes are allowed.
During Byte Writes, BWA controls DQA and BWB controls
DQB, BWC controls DQC, and BWD controls DQD. All I/Os
are three-stated during a Byte Write. Since this is a common
I/O device, the asynchronous OE input signal must be
deasserted and the I/Os must be three-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are three-stated once a Write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
1
, CE
2
, and CE
3
are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the Write input signals (GW, BWE, and
BW[A:D]) indicate a write access. ADSC is ignored if ADSP is
active LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ[D:A] will be
written into the specified address location. Byte Writes are
allowed. During byte writes, BWA controls DQA, BWB controls
DQB, BWC controls DQC, and BWD controls DQD. All I/Os
are three-stated when a Write is detected, even a Byte Write.
Since this is a common I/O device, the asynchronous OE input
signal must be deasserted and the I/Os must be three-stated
prior to the presentation of data to DQs. As a safety
precaution, the data lines are three-stated once a Write cycle
is detected, regardless of the state of OE.
Burst Sequences
The CY7C1344F provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
A[1:0], and can follow either a linear or interleaved burst order.
The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to a inter-
leaved burst sequence.
Page 4 of 15
CY7C1344F
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of t
ZZREC
after the ZZ input returns
LOW.
Linear Burst Address Table (MODE = GND)
First
Address
A
1
, A
0
00
01
10
11
Second
Address
A
1
, A
0
01
10
11
00
Third
Address
A
1
, A
0
10
11
00
01
Fourth
Address
A
1
, A
0
11
00
01
10
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
00
11
10
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
Test Conditions
ZZ > V
DD
– 0.2V
ZZ > V
DD
– 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
0
2t
CYC
2t
CYC
Min.
Max.
40
2t
CYC
Unit
mA
ns
ns
ns
ns
Truth Table
[2, 3, 4, 5, 6]
Cycle Description
Deselected Cycle,
Power-down1
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Snooze Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Address
Used
None
None
None
None
None
None
External
External
CE
1
CE
3
CE
2
H
L
L
L
X
X
L
L
X
X
H
X
X
X
L
L
X
L
X
L
X
X
H
H
ZZ
L
L
L
L
L
H
L
L
ADSP
X
L
L
H
H
X
L
L
ADSC
L
X
X
L
L
X
X
X
ADV WRITE OE CLK
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
DQ
L-H Three-State
L-H Three-State
L-H Three-State
L-H Three-State
L-H Three-State
X
Three-State
L-H Q
L-H Three-State
Notes:
2. X = “Don't Care.” H =Logic HIGH, L =Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BW
A
, BW
B
, BW
C
, BW
D
) and BWE = L or GW= L. WRITE = H when all Byte Write Enable signals
(BW
A
, BW
B
, BW
C
, BW
D
), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
[A: D]
. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the Write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Three-State when
OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
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