PRELIMINARY
CY7C1380A
CY7C1382A
512K x 36 / 1M x 18 Pipelined SRAM
Features
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•
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Fast clock speed: 167, 150, 133, 100 MHz
Provide high-performance 3-1-1-1 access rate
Fast OE access times: 3.4, 3.8, 4.2 and 5.0 ns
Optimal for depth expansion
3.3V (–5% / +10%) power supply
Common data inputs and data outputs
Byte Write Enable and Global Write control
Chip enable for address pipeline
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• High-density, high-speed packages
inputs, address-pipelining Chip Enable (CE), burst control in-
puts (ADSC, ADSP, and ADV), write enables (BWa, BWb,
BWc, BWd and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data (DQ
a,b,c,d
) and the data
parity (DQP
a,b,c,d
) outputs, enabled by OE, are also asynchro-
nous.
DQ
a,b,c,d
and DQP
a,b,c,d
apply to CY7C1380 and DQ
a,b
and
DQP
a,b
apply to CY7C1382. a, b, c, d each are 8 bits wide in
the case of DQ and 1 bit wide in the case of DP.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa and DQPa. BWb controls DQb and DQPb. BWc
controls DQcand DQPd. BWd controls DQd-DQd and DQPd.
BWa, BWb, BWc, and BWd can be active only with BWE being
LOW. GW being LOW causes all bytes to be written. WRITE
pass-through capability allows written data available at the out-
put for the immediately next READ cycle. This device also in-
corporates pipelined enable circuit for easy depth expansion
without penalizing system performance.
All inputs and outputs of the CY7C1380A and the CY7C1382A
are JEDEC standard JESD8-5 compatible.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced tri-
ple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
The CY7C1380A and CY7C1382A SRAMs integrate
524,288x36 and 1,048,576x18 SRAM cells with advanced
synchronous peripheral circuitry and a 2-bit counter for inter-
nal burst operation. All synchronous inputs are gated by reg-
isters controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
Selection Guide
167 MHz
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Shaded areas contain advance information.
150 MHz
3.8
310
30
133 MHz
4.2
280
30
100 MHz
5.0
250
30
3.4
Commercial
350
30
Cypress Semiconductor Corporation
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3901 North First Street
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San Jose
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CA 95134
•
408-943-2600
May 18, 2000
PRELIMINARY
Pin Definitions (100-Pin TQFP)
x18 Pin Locations x36 Pin Locations
37, 36, 32–25,
37, 36, 32–35,
42–50, 80–82, 99, 42–50, 81, 82, 99,
100
100
Name
A0
A1
A
I/O
Input-
Synchronous
CY7C1380A
CY7C1382A
93, 94
93, 94, 95, 96,
88
88
BWa
BWb
BWc
BWd
GW
Input-
Synchronous
Description
Address Inputs used to select one of the address
locations. Sampled at the rising edge of the CLK if
ADSP or ADSC is active LOW, and CE
1,
CE
2
, and
CE
3
are sampled active. A
[1:0]
feed the 2-bit
counter.
Byte Write Select Inputs, active LOW. Qualified with
BWE to conduct byte writes to the SRAM. Sampled
on the rising edge of CLK.
Global Write Enable Input, active LOW. When as-
serted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regard-
less of the values on BW
a,b,c,d
and BWE).
Byte Write Enable Input, active LOW. Sampled on
the rising edge of CLK. This signal must be assert-
ed LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs
to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst
operation.
Chip Enable 1 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ig-
nored if CE
1
is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the
rising edge of CLK. Used in conjunction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
1
and CE
2
to select/deselect the device.
Output Enable, asynchronous input, active LOW.
Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a
read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge
of CLK. When asserted, it automatically increments
the address in a burst cycle.
Address Strobe from Processor, sampled on the
rising edge of CLK. When asserted LOW, A is cap-
tured in the address registers. A
[1:0]
are also loaded
into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized. ASDP is
ignored when CE
1
is deasserted HIGH.
Input-
Synchronous
87
87
BWE
Input-
Synchronous
Input-Clock
89
89
CLK
98
98
CE
1
Input-
Synchronous
97
97
CE
2
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
92
92
CE
3
86
86
OE
83
83
ADV
Input-
Synchronous
Input-
Synchronous
84
84
ADSP
5
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