• Phase-locked loop clock distribution for Double Data
Rate Synchronous DRAM applications
• Distributes one clock input to ten differential outputs
• External feedback pin (FBIN) is used to synchronize the
outputs to the clock input
• Conforms to the DDR1 specification
• Spread Aware™ for EMI reduction
• 48-pin SSOP package
Description
This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD
operation and differential outputs levels.
This device is a zero delay buffer that distributes a clock input
(CLKIN) to ten differential pairs of clock outputs (YT[0:9],
YC[0:9]) and one feedback clock output (FBOUT). The clock
outputs are individually controlled by the serial inputs SCLK
and SDATA.
The two line serial bus can set each output clock pair (YT[0:9],
YC[0:9]) to the Hi-Z state. When AVDD is grounded, the PLL
is turned off and bypassed for the test purposes.
The PLL in this device uses the input clock (CLKIN) and the
feedback clock (FBIN) to provide high-performance, low-skew,
low-jitter output differential clocks.
Block Diagram
Pin Configuration
10
YT0
YC0
YT1
YC1
YT2
YC2
SCLK
SDATA
YT4
YC4
YT5
YC5
YT6
YC6
CLKIN
PLL
FBIN
YT7
YC7
YT8
YC8
YT9
YC9
CY28357
Serial
Interface
Logic
YT3
YC3
AVDD
FBOUT
NC
YC0
YT0
VDDQ
YT1
YC1
VSS
VSS
YC2
YT2
VDD
SCLK
CLKIN
NC
VDDQ
AVDD
AVSS
VSS
YC3
YT3
VDDQ
YT4
YC4
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VSS
YC5
YT5
VDDQ
YT6
YC6
VSS
VSS
YC7
YT7
VDDQ
SDATA
NC
FBIN
VDDQ
FBOUT
NC
VSS
YC8
YT8
VDDQ
YT9
YC9
VSS
Cypress Semiconductor Corporation
Document #: 38-07416 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 27, 2002
PRELIMINARY
Pin Description
[1]
Pin
13
35
3, 5, 10, 20, 22
46, 44, 39, 29,27
2, 6, 9, 19, 23
47, 43, 40,30,26
33
Name
CLKIN
FBIN
YT(0:9)
YC(0:9)
FBOUT
I/O
I
I
O
O
O
Clock Input.
Feedback Clock Input.
Connect to FBOUT for
accessing the PLL.
Clock Outputs
Clock Outputs
Feedback Clock Output.
Connect to FBIN for
normal operation. A bypass delay capacitor at
this output will control Input Reference/Output
Clocks phase relationships.
Serial Clock Input.
Clocks data at SDATA into
the internal register.
Serial Data Input.
Input data is clocked to the
internal register to enable/disable individual
outputs. This provides flexibility in power
management.
2.5V Power Supply for Logic
2.5V Power Supply for Output Clock Buffers.
2.5V Power Supply for PLL
No Connect
Common Ground
Analog Ground
Not Connected
0.0V Ground
0.0V Analog Ground
Output
Description
CY28357
Electrical Characteristics
Input
Input
Differential Outputs
12
37
SCLK
SDATA
I
I/O
Data Input for the two line serial bus
Data Input and Output for the two
line serial bus
11
4, 15, 21, 28, 34,
38, 45
16
1, 24
7, 8, 18, 25, 31, 41,
42, 48
17
14,32,36
VDD
VDDQ
AVDD
NC
VSS
AVSS
NC
2.5V Nominal
2.5V Nominal
2.5V Nominal
Note:
1. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Document #: 38-07416 Rev. *A
Page 2 of 12
PRELIMINARY
Function Table
Input
VDDA
GND
GND
2.5V
2.5V
2.5V
CLKIN
L
H
L
H
< 20 MHz
YT(0:9)
[2]
L
H
L
H
Hi-Z
Outputs
YC(0:9)
[2]
H
L
H
L
Hi-Z
FBOUT
L
H
L
H
Hi-Z
PLL
CY28357
BYPASSED/OFF
BYPASSED/OFF
On
On
Off
Zero Delay Buffer
When used as a zero delay buffer the CY28357 will likely be
in a nested clock tree application. For these applications the
CY28357 offers a clock input as a PLL reference. The
CY28357 then can lock onto the reference and translate with
near zero delay to low-skew outputs. For normal operation, the
external feedback input, FBIN, is connected to the feedback
output, FBOUT. By connecting the feedback output to the
feedback input the propagation delay through the device is
eliminated. The PLL works to align the output edge with the
input reference edge thus producing a near zero delay. The
reference frequency affects the static phase offset of the PLL
and thus the relative delay between the inputs and outputs.
Note:
2. Each output pair can be three-stated via the two line serial interface
When VDDA is strapped LOW, the PLL is turned off and by-
passed for test purposes.
Power Management
The individual output enable/disable control of the CY28357
allows the user to implement unique power management
schemes into the design. Outputs are three-stated when dis-
abled through the two-line interface as individual bits are set
low in Byte0 and Byte1 registers. The feedback output
(FBOUT) cannot be disabled via two line serial bus. The en-
abling and disabling of individual outputs is done in such a
manner as to eliminate the possibility of partial “runt” clocks.
Document #: 38-07416 Rev. *A
Page 3 of 12
PRELIMINARY
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface initial-
ize to their default setting upon power-up, and therefore use of
this interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface can also be used during system operation for
power management functions.
T
CY28357
Data Protocol
The clock driver serial protocol accepts block write, and block
read operations from the controller. For block write/read oper-
ation, the bytes must be accessed in sequential order from
lowest to highest byte (most significant bit first) with the ability
to stop after any complete byte has been transferred. The
block write and block read protocol is outlined in
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