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CY7C1413JV18
CY7C1415JV18
36-Mbit QDR
®
II SRAM 4-Word
Burst Architecture
Features
■
Configurations
CY7C1413JV18 – 2M × 18
CY7C1415JV18 – 1M × 36
Separate independent read and write data ports
❐
Supports concurrent transactions
300-MHz clock for high bandwidth
4-word burst for reducing address bus frequency
Double data rate (DDR) interfaces on both read and write ports
(data transferred at 600 MHz) at 300 MHz
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Single multiplexed address input bus latches address inputs
for both read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
Quad data rate (QDR) II operates with 1.5-cycle read latency
when DLL is enabled
Operates similar to a QDR I device with 1-cycle read latency
in delay lock loop (DLL) off mode
Available in ×18, and ×36 configurations
Full data coherency, providing most current data
Core V
DD
= 1.8 (± 0.1 V); I/O V
DDQ
= 1.4 V to V
DD
Available in 165-ball fine pitch ball grid array (FBGA) package
(15 × 17 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
Variable drive high-speed transceiver logic (HSTL) output
buffers
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
■
■
■
■
Functional Description
The CY7C1413JV18 and CY7C1415JV18 are 1.8-V
synchronous pipelined SRAMs, equipped with QDR
®
II
architecture. QDR II architecture consists of two separate ports
to access the memory array. The read port has dedicated data
outputs to support the read operations and the write port has
dedicated data inputs to support the write operations. QDR II
architecture has separate data inputs and data outputs to
completely eliminate the need to “turnaround” the data bus
required with common I/O devices. Access to each port is
through a common address bus. Addresses for read and write
addresses are latched on alternate rising edges of the input (K)
clock. Accesses to the QDR II read and write ports are
completely independent of one another. To maximize data
throughput, read and write ports are equipped with DDR
interfaces. Each address location is associated with four 18-bit
words (CY7C1413JV18), or 36-bit words (CY7C1415JV18) that
burst sequentially into or out of the device. Because data can be
transferred into and out of the device on every rising edge of both
input clocks (K and K and C and C), memory bandwidth is
maximized while simplifying system design by eliminating bus
“turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Selection Guide
Description
Maximum operating frequency
Maximum operating current
×18
×36
300 MHz
300
1010
1130
250 MHz
250
790
870
200 MHz
200
655
715
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 001-12557 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 13, 2010
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CY7C1413JV18
CY7C1415JV18
Logic Block Diagram (CY7C1413JV18)
D
[17:0]
18
Read Add. Decode
Write Add. Decode
A
(18:0)
19
Write
Reg
Address
Register
Write
Reg
Write
Reg
Write
Reg
Address
Register
19
A
(18:0)
512K x 18 Array
512K x 18 Array
512K x 18 Array
512K x 18 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
CQ
DOFF
Read Data Reg.
72
V
REF
WPS
BWS
[1:0]
36
Control
Logic
36
Reg.
Reg.
Reg. 18
18
18
18
CQ
18
Q
[17:0]
Logic Block Diagram (CY7C1415JV18)
D
[35:0]
36
Read Add. Decode
Write Add. Decode
A
(17:0)
18
Write
Reg
Address
Register
Write
Reg
Write
Reg
Write
Reg
Address
Register
18
A
(17:0)
256K x 36 Array
256K x 36 Array
256K x 36 Array
256K x 36 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
CQ
DOFF
Read Data Reg.
144
V
REF
WPS
BWS
[3:0]
72
Control
Logic
72
Reg.
Reg.
Reg. 36
36
36
36
CQ
36
Q
[35:0]
Document Number: 001-12557 Rev. *F
Page 2 of 26
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CY7C1413JV18
CY7C1415JV18
Contents
Pin Configuration ............................................................. 4
165-Ball FBGA (15 × 17 × 1.4 mm) Pinout.................. 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 7
Read Operations ......................................................... 7
Write Operations ......................................................... 7
Byte Write Operations ................................................. 7
Single Clock Mode ...................................................... 7
Concurrent Transactions ............................................. 7
Depth Expansion ......................................................... 8
Programmable Impedance .......................................... 8
Echo Clocks ................................................................ 8
DLL.............................................................................. 8
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Write Cycle Descriptions ................................................. 9
Write Cycle Descriptions ............................................... 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port—Test Clock................................... 11
Test Mode Select (TMS) ........................................... 11
Test Data-In (TDI) ..................................................... 11
Test Data-Out (TDO)................................................. 11
Performing a TAP Reset ........................................... 11
TAP Registers ........................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Electrical Characteristics ...................................... 14
TAP AC Switching Characteristics ............................... 15
TAP Timing and Test Conditions ..................................
Identification Register Definitions ................................
Scan Register Sizes .......................................................
Instruction Codes...........................................................
Boundary Scan Order ....................................................
Power Up Sequence in QDR II SRAM ...........................
Power Up Sequence .................................................
DLL Constraints ........................................................
Maximum Ratings...........................................................
Operating Range ............................................................
Electrical Characteristics ..............................................
DC Electrical Characteristics.....................................
AC Electrical Characteristics.....................................
Capacitance ....................................................................
Thermal Resistance .......................................................
Switching Characteristics .............................................
Switching Waveforms ....................................................
Ordering Information .....................................................
Ordering Code Definition...........................................
Package Diagram ...........................................................
Document History Page.................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC Solutions .........................................................
15
16
16
16
17
18
18
18
19
19
19
19
20
20
20
21
22
23
23
24
25
26
26
26
26
Document Number: 001-12557 Rev. *F
Page 3 of 26
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CY7C1413JV18
CY7C1415JV18
Pin Configuration
The pin configuration for CY7C1413JV18, and CY7C1415JV18 follows.
[1]
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1413JV18 (2M x 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/144M
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
A
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/288M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
NC/72M
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
CY7C1415JV18 (1M x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
2
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
BWS
1
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
A
10
NC/144M
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
NC/288M NC/72M
Note
1. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-12557 Rev. *F
Page 4 of 26
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