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CY7C1475V33-100BGI

产品描述ZBT SRAM, 1MX72, 8.5ns, CMOS, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FBGA-209
产品类别存储    存储   
文件大小375KB,共30页
制造商Cypress(赛普拉斯)
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CY7C1475V33-100BGI概述

ZBT SRAM, 1MX72, 8.5ns, CMOS, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FBGA-209

CY7C1475V33-100BGI规格参数

参数名称属性值
是否Rohs认证不符合
零件包装代码BGA
包装说明14 X 22 MM, 1.76 MM HEIGHT, FBGA-209
针数209
Reach Compliance Codecompliant
ECCN代码3A991.B.2.A
最长访问时间8.5 ns
其他特性FLOW-THROUGH ARCHITECTURE
JESD-30 代码R-PBGA-B209
JESD-609代码e0
长度22 mm
内存密度75497472 bit
内存集成电路类型ZBT SRAM
内存宽度72
功能数量1
端子数量209
字数1048576 words
字数代码1000000
工作模式SYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织1MX72
封装主体材料PLASTIC/EPOXY
封装代码BGA
封装形状RECTANGULAR
封装形式GRID ARRAY
并行/串行PARALLEL
峰值回流温度(摄氏度)NOT SPECIFIED
认证状态Not Qualified
座面最大高度1.96 mm
最大供电电压 (Vsup)3.63 V
最小供电电压 (Vsup)3.135 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin/Lead (Sn/Pb)
端子形式BALL
端子节距1 mm
端子位置BOTTOM
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度14 mm
Base Number Matches1

文档预览

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PRELIMINARY
CY7C1471V33
CY7C1473V33
CY7C1475V33
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through
SRAM with NoBL™ Architecture
Features
• No Bus Latency™ (NoBL™) architecture eliminates
dead cycles between write and read cycles.
• Can support up to 133-MHz bus operations with zero
wait states
• Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 3.3V/2.5V I/O power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 8.5 ns (for 100-MHz device)
• Clock Enable (CEN) pin to enable clock and suspend
operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Offered in JEDEC-standard lead-free 100 TQFP, and
165-ball fBGA packages for CY7C1471V33 and
CY7C1473V33. Lead-free 209-ball fBGA package for
CY7C1475V33.
• Three chip enables for simple depth expansion.
• Automatic Power-down feature available using ZZ
mode or CE deselect.
• JTAG boundary scan for BGA and fBGA packages
• Burst Capability—linear or interleaved burst order
• Low standby power
Functional Description
[1]
The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are
3.3V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through
Burst SRAMs designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1471V33, CY7C1473V33 and
CY7C1475V33 are equipped with the advanced No Bus
Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BW
X
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Selection Guide
133 MHz
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
6.5
335
150
100 MHz
8.5
305
150
Unit
ns
mA
mA
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05288 Rev. *G
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised March 10, 2005

CY7C1475V33-100BGI相似产品对比

CY7C1475V33-100BGI CY7C1471V33-100BZXI CY7C1471V33-100BZI CY7C1473V33-100BZXI CY7C1475V33-100BGXI CY7C1471V33-100AXI CY7C1473V33-100AXI CY7C1473V33-100BZI
描述 ZBT SRAM, 1MX72, 8.5ns, CMOS, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FBGA-209 ZBT SRAM, 2MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165 ZBT SRAM, 2MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165 ZBT SRAM, 4MX18, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165 ZBT SRAM, 1MX72, 8.5ns, CMOS, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, LEAD FREE, FBGA-209 ZBT SRAM, 2MX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, TQFP-100 ZBT SRAM, 4MX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, TQFP-100 ZBT SRAM, 4MX18, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165
是否Rohs认证 不符合 符合 不符合 符合 符合 符合 符合 不符合
零件包装代码 BGA BGA BGA BGA BGA QFP QFP BGA
包装说明 14 X 22 MM, 1.76 MM HEIGHT, FBGA-209 LBGA, 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165 LBGA, BGA, LQFP, LQFP, 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165
针数 209 165 165 165 209 100 100 165
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant compliant
ECCN代码 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A
最长访问时间 8.5 ns 8.5 ns 8.5 ns 8.5 ns 8.5 ns 8.5 ns 8.5 ns 8.5 ns
其他特性 FLOW-THROUGH ARCHITECTURE FLOW-THROUGH ARCHITECTURE FLOW-THROUGH ARCHITECTURE FLOW-THROUGH ARCHITECTURE FLOW-THROUGH ARCHITECTURE FLOW-THROUGH ARCHITECTURE FLOW-THROUGH ARCHITECTURE FLOW-THROUGH ARCHITECTURE
JESD-30 代码 R-PBGA-B209 R-PBGA-B165 R-PBGA-B165 R-PBGA-B165 R-PBGA-B209 R-PQFP-G100 R-PQFP-G100 R-PBGA-B165
JESD-609代码 e0 e1 e0 e1 e1 e3 e3 e0
长度 22 mm 17 mm 17 mm 17 mm 22 mm 20 mm 20 mm 17 mm
内存密度 75497472 bit 75497472 bit 75497472 bit 75497472 bit 75497472 bit 75497472 bit 75497472 bit 75497472 bit
内存集成电路类型 ZBT SRAM ZBT SRAM ZBT SRAM ZBT SRAM ZBT SRAM ZBT SRAM ZBT SRAM ZBT SRAM
内存宽度 72 36 36 18 72 36 18 18
功能数量 1 1 1 1 1 1 1 1
端子数量 209 165 165 165 209 100 100 165
字数 1048576 words 2097152 words 2097152 words 4194304 words 1048576 words 2097152 words 4194304 words 4194304 words
字数代码 1000000 2000000 2000000 4000000 1000000 2000000 4000000 4000000
工作模式 SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C
最低工作温度 -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
组织 1MX72 2MX36 2MX36 4MX18 1MX72 2MX36 4MX18 4MX18
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 BGA LBGA LBGA LBGA BGA LQFP LQFP LBGA
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 GRID ARRAY GRID ARRAY, LOW PROFILE GRID ARRAY, LOW PROFILE GRID ARRAY, LOW PROFILE GRID ARRAY FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE GRID ARRAY, LOW PROFILE
并行/串行 PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
峰值回流温度(摄氏度) NOT SPECIFIED 260 220 260 260 260 260 220
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 1.96 mm 1.4 mm 1.4 mm 1.4 mm 1.96 mm 1.6 mm 1.6 mm 1.4 mm
最大供电电压 (Vsup) 3.63 V 3.63 V 3.63 V 3.63 V 3.63 V 3.63 V 3.63 V 3.63 V
最小供电电压 (Vsup) 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V
标称供电电压 (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
表面贴装 YES YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
端子面层 Tin/Lead (Sn/Pb) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Lead (Sn/Pb) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu) Matte Tin (Sn) MATTE TIN Tin/Lead (Sn/Pb)
端子形式 BALL BALL BALL BALL BALL GULL WING GULL WING BALL
端子节距 1 mm 1 mm 1 mm 1 mm 1 mm 0.65 mm 0.65 mm 1 mm
端子位置 BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM QUAD QUAD BOTTOM
处于峰值回流温度下的最长时间 NOT SPECIFIED 20 NOT SPECIFIED 20 20 40 40 NOT SPECIFIED
宽度 14 mm 15 mm 15 mm 15 mm 14 mm 14 mm 14 mm 15 mm
厂商名称 - Cypress(赛普拉斯) Cypress(赛普拉斯) Cypress(赛普拉斯) Cypress(赛普拉斯) Cypress(赛普拉斯) Cypress(赛普拉斯) Cypress(赛普拉斯)
湿度敏感等级 - 3 3 3 3 3 3 3
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