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CY7C1011DV33
2-Mbit (128 K × 16) Static RAM
2-Mbit (128 K × 16) Static RAM
Features
■
■
Functional Description
The CY7C1011DV33
[1]
is a high-performance CMOS Static
RAM organized as 128 K words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
16
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1011DV33 is available in standard Pb-free 44-pin
TSOP II with center power and ground pinout, as well as
48-ball very fine-pitch ball grid array (VFBGA) packages.
Pin-and function-compatible with CY7C1011CV33
High speed
❐
t
AA
= 10 ns
Low active power
❐
I
CC
= 90 mA @ 10 ns (Industrial)
Low CMOS standby power
❐
I
SB2
= 10 mA
Data Retention at 2.0 V
Automatic power-down when deselected
Independent control of upper and lower bits
Easy memory expansion with CE and OE features
Available in Pb-free 44-pin TSOP II, and 48-ball VFBGA
■
■
■
■
■
■
■
Logic Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
128K X 16
COLUMN
DECODER
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
BHE
WE
CE
OE
BLE
Note
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at
www.cypress.com
Cypress Semiconductor Corporation
Document Number: 38-05609 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 1, 2010
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CY7C1011DV33
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 4
Thermal Resistance .......................................................... 4
AC Test Loads and Waveforms ....................................... 5
AC Switching Characteristics ......................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Waveforms ...................................................... 7
Read Cycle No. 1 ........................................................ 7
Read Cycle No. 2 (OE Controlled) .............................. 7
Write Cycle No. 1 (CE Controlled) ............................... 8
Write Cycle No. 3 (WE Controlled,
OE HIGH During Write) ...................................................... 9
Write Cycle No. 4 (WE Controlled, OE LOW) ............. 9
Truth Table ...................................................................... 10
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagrams .......................................................... 11
Acronyms ........................................................................ 12
Document Conventions ................................................. 12
Units of Measure ....................................................... 12
Document History ........................................................... 13
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC Solutions ......................................................... 14
Document Number: 38-05609 Rev. *E
Page 2 of 14
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CY7C1011DV33
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
–10
10
90
10
Unit
ns
mA
mA
Pin Configurations
TSOP II
Top View
A
4
A
3
A
2
A
1
A
0
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
16
A
15
A
14
A
13
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
8
A
9
A
10
A
11
NC
48-ball VFBGA
(Top View)
1
BLE
I/O
8
I/O
9
V
SS
V
CC
I/O
14
I/O
15
NC
2
OE
BHE
I/O
10
3
A
0
A
3
A
5
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
NC
I/O
0
I/O
2
V
CC
V
SS
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
I/O
11
NC
I/O
12
I/O
13
NC
A
8
NC
A
14
A
12
A
9
Document Number: 38-05609 Rev. *E
Page 3 of 14
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CY7C1011DV33
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65
C
to +150
C
Ambient temperature with
power applied ........................................... –55
C
to +125
C
Supply voltage on V
CC
to relative GND
[3]
.....–0.3 V to +4.6 V
DC voltage applied to outputs
in high Z State
[3]
.................................. –0.3 V to V
CC
+ 0.3 V
DC input voltage
[3]
............................... –0.3 V to V
CC
+ 0.3 V
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage............ ...............................> 2001 V
(per MIL-STD-883, method 3015)
Latch-up current ..................................................... > 200 mA
Operating Range
Range
Industrial
Ambient
Temperature
–40
C
to +85
C
V
CC
3.3 V
0.3 V
DC Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
[2]
Input leakage current
Output leakage current
V
CC
operating supply current
GND < V
I
< V
CC
GND < V
OUT
< V
CC
, Output Disabled
V
CC
= Max, f = f
MAX
= 1/t
RC
100 MHz
83 MHz
66 MHz
40 MHz
I
SB1
I
SB2
Automatic CE Power-down
Current — TTL Inputs
Automatic CE Power-down
Current — CMOS Inputs
Max V
CC
, CE > V
IH
, V
IN
> V
IH
or V
IN
< V
IL
,
f = f
MAX
Max V
CC
, CE > V
CC
– 0.3 V,
V
IN
> V
CC
– 0.3 V, or V
IN
< 0.3 V, f = 0
Test Conditions
V
CC
= Min, I
OH
= –4.0 mA
V
CC
= Min, I
OL
= 8.0 mA
–10
Min
2.4
–
2.0
–0.3
–1
–1
–
–
–
–
–
–
Max
–
0.4
V
CC
+ 0.3
0.8
+1
+1
90
80
70
60
20
10
mA
mA
Unit
V
V
V
V
A
A
mA
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input capacitance
I/O capacitance
Test Conditions
T
A
= 25
C,
f = 1 MHz, V
CC
= 3.3 V
Max
8
8
Unit
pF
pF
Thermal Resistance
[3]
Parameter
JA
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
TSOP II
50.66
17.17
VFBGA
27.89
14.74
Unit
C/W
C/W
Notes
2. V
IL
(min) = –2.0 V and V
IH
(max) = V
CC
+ 2 V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05609 Rev. *E
Page 4 of 14
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