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CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
FLEx36™ 3.3V 32K/64K/128K/256K/512 x 36
Synchronous Dual-Port RAM
Features
■
■
■
■
■
■
■
Functional Description
The FLEx36™ family includes 1-Mbit, 2-Mbit, 4-Mbit, 9-Mbit, and
18-Mbit pipelined, synchronous, true dual-port static RAMs that
are high speed, low power 3.3V CMOS. Two ports are provided,
permitting independent, simultaneous access to any location in
memory. A particular port can write to a certain location while
another port is reading that location. The result of writing to the
same location by more than one port at the same time is
undefined. Registers on control, address, and data lines allow for
minimal setup and hold time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CYD18S36V devices in this family has limited features.
Please see Address Counter and Mask Register Operations
[19]
on page 5 for details.
True dual-ported memory cells that enable simultaneous
access of the same memory location
Synchronous pipelined operation
Family of 1-Mbit, 2-Mbit, 4-Mbit, 9-Mbit and 18-Mbit devices
Pipelined output mode allows fast operation
0.18 micron CMOS for optimum speed and power
High speed clock to data access
3.3V low power
❐
Active as low as 225 mA (typ.)
❐
Standby as low as 55 mA (typ.)
Mailbox function for message passing
Global master reset
Separate byte enables on both ports
Commercial and industrial temperature ranges
IEEE 1149.1-compatible JTAG boundary scan
256 Ball FBGA (1-mm pitch)
Counter wrap around control
❐
Internal mask register controls counter wrap-around
❐
Counter-interrupt flags to indicate wrap-around
❐
Memory block retransmit operation
Counter readback on address lines
Mask register readback on address lines
Dual Chip Enables on both ports for easy depth expansion
Seamless migration to next-generation dual-port family
■
■
■
■
■
■
■
■
■
■
■
Seamless Migration to Next-Generation Dual-Port
Family
Cypress offers a migration path for all devices in this family to the
next-generation devices in the Dual-Port family with a compatible
footprint. Please contact Cypress Sales for more details.
Table 1. Product Selection Guide
Density
Part Number
Max. Speed (MHz)
Max. Access Time – Clock to Data
(ns)
Typical Operating Current (mA)
Package
1 Mbit
(32K x 36)
CYD01S36V
167
4.0
225
2 Mbit
(64K x 36)
CYD02S36V/36VA
167
4.4
225
4 Mbit
(128K x 36)
CYD04S36V
167
4.0
225
9 Mbit
(256K x 36)
CYD09S36V
167
4.0
270
18 Mbit
(512K x 36)
CYD18S36V
133
5.0
315
256 FBGA
256 FBGA
256 FBGA
256 FBGA
256 FBGA
(17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm) (23 mm x 23 mm)
Cypress Semiconductor Corporation
Document Number: 38-06076 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised Decenber 09, 2008
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CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Logic Block Diagram
[1]
FTSEL
L
CONFIG Block
PORTSTD[1:0]
L
CONFIG Block
PORTSTD[1:0]
R
FTSEL
R
DQ [35:0]
L
BE [3:0]
L
CE0
L
CE1
L
OE
L
R/W
L
IO
Control
IO
Control
DQ [35:0]
R
BE [3:0]
R
CE0
R
CE1
R
OE
R
R/W
R
Dual Ported Array
BUSY
L
A [18:0]
L
CNT/MSK
L
ADS
L
CNTEN
L
CNTRST
L
RET
L
CNTINT
L
C
L
WRP
L
Arbitration Logic
BUSY
R
A [18:0]
R
CNT/MSK
R
ADS
R
CNTEN
R
CNTRST
R
RET
R
CNTINT
R
C
R
WRP
R
Address &
Counter Logic
Address &
Counter Logic
Mailboxes
INT
L
INT
R
JTAG
TRST
TMS
TDI
TDO
TCK
READY
L
LowSPD
L
RESET
LOGIC
MRST
READY
R
LowSPD
R
Note
1. 18-Mbit device has 19 address bits, 9-Mbit device has 18 address bits, 4-Mbit device has 17 address bits, 2-Mbit device has 16 address bits, and 1-Mbit device has
15 address bits.
Document Number: 38-06076 Rev. *G
Page 2 of 28
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CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Pin Configurations
Figure 1. Pin Diagram - 256-Ball FBGA (Top View)
CYD01S36V/CYD02S36V/36VA/CYD04S36V/CYD09S36V/CYD18S36V
1
2
DQ30L
DQ31L
DQ35L
A1L
A3L
A5L
A7L
A9L
A11L
A13L
A15L
[6]
A17L
[8]
A19L
[2,5]
DQ17L
DQ13L
DQ12L
3
DQ28L
DQ29L
RETL
[2,3]
WRPL
[2,3]
CE0L
[11]
CNTINT
L [12]
BUSYL
[2,5]
CL
VSS
OEL
ADSL
[11]
R/WL
4
DQ26L
DQ27L
INTL
5
DQ24L
DQ25L
NC
[2,5]
6
DQ22L
DQ23L
NC
[2,5]
7
DQ20L
DQ21L
REVL
[2,4]
VSS
8
DQ18L
DQ19L
TRST
[2,5]
VTTL
9
DQ18R
DQ19R
MRST
VTTL
10
DQ20R
DQ21R
NC
[2,5]
VSS
VDDIO
R
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
R
REV
R
[2,3]
TDI
DQ3R
DQ2R
11
DQ22R
DQ23R
NC
[2,5]
12
DQ24R
DQ25R
NC
[2,5]
13
DQ26R
DQ27R
INTR
14
DQ28R
DQ29R
RETR
[2,3]
WRPR
[2,3]
CE0R
[11]
CNTINT
R [12]
BUSYR
[2,5]
CR
VSS
OER
ADSR
[11]
R/WR
CNT/M
SKR
[10]
15
DQ30R
DQ31R
DQ35R
A1R
A3R
A5R
A7R
A9R
A11R
A13R
A15R
[6]
A17R
[8]
A19R
[2,5]
16
DQ32R
DQ33R
DQ34R
A0R
A2R
A4R
A6R
A8R
A10R
A12R
A14R
A16R
[7]
A18R
[9]
DQ16R
DQ15R
DQ14R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
DQ32L
DQ33L
DQ34L
A0L
A2L
A4L
A6L
A8L
A10L
A12L
A14L
A16L
[7]
A18L
[9]
DQ16L
DQ15L
DQ14L
VREFL FTSELL LOWSP
[2,4]
[2,3]
DL [2,4]
CE1L
[10]
BE3L
BE2L
VTTL
LOWSP FTSEL VREFL
[2,4]
DR [2,4] R [2,3]
VDDIO
R
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
R
READY
R [2,5]
NC
[2,5]
DQ5R
DQ4R
VDDIO
R
VDDIO
R
VDDIO
R
VCORE
CE1R
[10]
BE3R
BE2R
VTTL
VDDIOL VDDIOL VDDIOL VCORE VCORE
VDDIOL
REV
L
[2,3]
VCORE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PORTS
TD1L[2, VCORE
4]
BE1L
BE0L
REVL
[2,4]
VDDIOL
VDDIOL
PORTS
VCORE TD1R[2,
4]
VDDIO
R
VDDIO
R
VDDIO
R
PortST
D0R
[2,4]
NC
[2,5]
DQ7R
DQ6R
BE1R
BE0R
REVR
[2,4]
VREFR
[2,4]
VDDIOL VDDIOL VDDIOL VCORE VCORE
PortST
D0L
[2,4]
NC
[2,5]
DQ7L
DQ6L
READY
L [2,5]
NC
[2,5]
DQ5L
DQ4L
REV
L
[2,3]
TCK
DQ3L
DQ2L
CNT/M VREFL
[2,4]
SKL [10]
CNTEN CNTRS
L [11]
TL [10]
DQ11L
DQ10L
DQ9L
DQ8L
VTTL
VTTL
TMS
DQ1L
DQ0L
TDO
DQ1R
DQ0R
CNTRS CNTEN
DQ17R
TR [10] R [11]
DQ9R
DQ8R
DQ11R
DQ10R
DQ13R
DQ12R
Notes
2. This ball represents a next generation Dual-Port feature. For more information about this feature, contact Cypress Sales.
3. Connect this ball to VDDIO. For more information about this next generation Dual-Port feature contact Cypress Sales.
4. Connect this ball to VSS. For more information about this next generation Dual-Port feature, contact Cypress Sales.
5. Leave this ball unconnected. For more information about this feature, contact Cypress Sales.
6. Leave this ball unconnected for 32K x 36configuration.
7. Leave this ball unconnected for a 64K x 36, 32K x 36 configurations.
8. Leave this ball unconnected for a 128K x 36, 64K x 36 and 32K x 36 configurations.
9. Leave this ball unconnected for a 256K x 36, 128K x 36, 64K x 36, and 32K x 36 configurations.
10. These balls are not applicable for CYD18S36V device. They need to be tied to VDDIO.
11. These balls are not applicable for CYD18S36V device. They need to be tied to VSS.
12. These balls are not applicable for CYD18S36V device. They need to be no connected.
Document Number: 38-06076 Rev. *G
Page 3 of 28
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CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Pin Definitions
Left Port
A
0L
–A
18L
BE
0L
–BE
3L
BUSY
L[2,5]
C
L
CE0
L[11]
CE1
L
[10]
Right Port
A
0R
–A
18R
BE
0R
–BE
3R
BUSY
R[2,5]
C
R
CE0
R[11]
CE1
R
[10]
Description
Address Inputs.
Byte Enable Inputs.
Asserting these signals enables Read and Write operations to the
corresponding bytes of the memory array.
Port Busy Output.
When the collision is detected, a BUSY is asserted.
Input Clock Signal.
Active Low Chip Enable Input.
Active High Chip Enable Input.
Data Bus Input/Output.
Output Enable Input.
This asynchronous signal must be asserted LOW to enable the DQ
data pins during Read operations.
Mailbox Interrupt Flag Output.
The mailbox permits communications between ports. The
upper two memory locations can be used for message passing. INT
L
is asserted LOW
when the right port writes to the mailbox location of the left port, and vice versa. An interrupt
to a port is deasserted HIGH when it reads the contents of its mailbox.
Port Low Speed Select Input.
Read/Write Enable Input.
Assert this pin LOW to write to, or HIGH to Read from the dual
port memory array.
Port Ready Output.
This signal is asserted when a port is ready for normal operation.
Port Counter/Mask Select Input.
Counter control input.
Port Counter Address Load Strobe Input.
Counter control input.
Port Counter Enable Input.
Counter control input.
Port Counter Reset Input.
Counter control input.
Port Counter Interrupt Output.
This pin is asserted LOW when the unmasked portion of
the counter is incremented to all “1s”.
Port Counter Wrap Input.
The burst counter wrap control input.
Port Counter Retransmit Input.
Counter control input.
Flow-Through Select.
Use this pin to select Flow-Through mode. When is de-asserted,
the device is in pipelined mode.
Port External High-Speed IO Reference Input.
Port IO Power Supply.
Reserved pins for future features.
Master Reset Input.
MRST is an asynchronous input signal and affects both ports. A
maser reset operation is required at power up.
JTAG Reset Input.
JTAG Test Mode Select Input.
It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
JTAG Test Data Input.
Data on the TDI input is shifted serially into selected registers.
JTAG Test Clock Input.
JTAG Test Data Output.
TDO transitions occur on the falling edge of TCK. TDO is
normally three-stated except when captured data is shifted out of the JTAG TAP.
Ground Inputs.
Core Power Supply.
LVTTL Power Supply for JTAG IOs
DQ
0L
–DQ
35L
OE
L
INT
L
DQ
0R
–DQ
35R
OE
R
INT
R
LowSPD
L[2,4]
R/W
L
READY
L[2,5]
CNT/MSK
L[10]
ADS
L[11]
CNTEN
L[11]
CNTRST
L[10]
CNTINT
L[12]
WRP
L[2,3]
RET
L
[2,3]
LowSPD
R[2,4]
R/W
R
READY
R[2,5]
CNT/MSK
R[10]
ADS
R[11]
CNTEN
R
[11]
[10]
PORTSTD[1:0]
L[2,4]
PORTSTD[1:0]
R[2,4]
Port Address/Control/Data IO Standard Select Inputs.
CNTRST
R
CNTINT
R
[12]
WRP
R[2,3]
RET
R[2,3]
FTSEL
R[2,3]
VREF
R[2,4]
V
DDIOR
REV
R[2, 3, 4]
MRST
TRST
[2,5]
TMS
TDI
TCK
TDO
V
SS
V
CORE[13]
V
TTL
FTSEL
L[2,3]
VREF
L[2,4]
V
DDIOL
REV
L
[2, 3, 4]
Document Number: 38-06076 Rev. *G
Page 4 of 28
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