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CY7C1366B-250BZC: 产品描述Cache SRAM, 256KX36, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165; 产品类别存储存储; 文件大小659KB，共27页; 制造商Cypress(赛普拉斯)

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CY7C1366B-250BZC概述

Cache SRAM, 256KX36, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165

CY7C1366B-250BZC规格参数

参数名称	属性值
是否Rohs认证	不符合
零件包装代码	BGA
包装说明	13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
针数	165
Reach Compliance Code	compliant
ECCN代码	3A991.B.2.A
最长访问时间	2.6 ns
其他特性	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)	250 MHz
I/O 类型	COMMON
JESD-30 代码	R-PBGA-B165
长度	15 mm
内存密度	9437184 bit
内存集成电路类型	CACHE SRAM
内存宽度	36
湿度敏感等级	1
功能数量	1
端子数量	165
字数	262144 words
字数代码	256000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	256KX36
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	TBGA
封装等效代码	BGA165,11X15,40
封装形状	RECTANGULAR
封装形式	GRID ARRAY, THIN PROFILE
并行/串行	PARALLEL
峰值回流温度（摄氏度）	225
电源	2.5/3.3,3.3 V
认证状态	Not Qualified
座面最大高度	1.2 mm
最大待机电流	0.03 A
最小待机电流	3.14 V
最大压摆率	0.25 mA
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	3.135 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	13 mm
Base Number Matches	1

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PRELIMINARY

CY7C1366B

CY7C1367B

256K x 36/512K x 18 Pipelined

Double-cycle Deselect SRAM

Features

• Supports bus operation up to 250 MHz

— Available speed grades are 250, 200, and 166 MHz

• Fully registered inputs and outputs for pipelined

operation

• Single 3.3V power supply

• Supports 3.3V and 2.5V I/Os

• Fast clock-to-output times

— 2.6ns (for 250 MHz device)

— 3.0ns (for 200 MHz device)

•

— 3.5 ns (for 166 MHz device)

User-selectable burst counter supporting Intel



Pentium

interleaved or linear burst sequences

Separate processor and controller address strobes

Synchronous self-timed writes

Asynchronous output enable

Two Cycle Chip Deselect

Available as a 100-pin TQFP, 119-Ball BGA, 165-Ball

FBGA

TQFP and FBGA has 3 Chip Enables

119 BGA has 2-Chip Enables

IEEE 1149.1 JTAG-compatible Boundary Scan for 119

BGA and 165 FBGA Packages

“ZZ” Sleep Mode option and Stop Clock option

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

Maximum access delay from the clock rise is 2.6 ns (250 MHz

device).

The CY7C1366B and CY7C1367B support either the inter-

leaved burst sequence used by the Intel Pentium processor or

a linear burst sequence used by processors such as the

PowerPC™. The burst sequence is selected through the

MODE pin (Pin 31 and ball R3 for the TQFP and BGA

packages, respectively.) Accesses can be initiated by

asserting either the Processor Address Strobe (ADSP) or the

Controller Address Strobe (ADSC) at clock rise. Address

advancement through the burst sequence is controlled by the

ADV input. A 2-bit on-chip wraparound burst counter captures

the first address in a burst sequence and automatically incre-

ments the address for the rest of the burst access.

Byte write operations are qualified with the Byte Write Select

(BW

a,b,c,d

for 1366B and BW

a,b

for 1367B) inputs. A Global

Write Enable (GW) overrides all byte write inputs and writes

data to all four bytes. All writes are conducted with on-chip

synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to provide

proper data during depth expansion, OE is masked during the

first clock of a read cycle when emerging from a deselected

state.

Functional Description

The CY7C1366B and CY7C1367B are 3.3V, 256K x 36 and

512K x 18 synchronous-pipelined cache SRAM, respectively.

Logic Block Diagram

CLK

ADV

DQP

1366B

[17:0]

a,b,c,d

DQP

a,b,c,d

1367B

[18:0]

a,b

DQP

a,b

BWE

MODE

ADSP

ADSC

CONTROL

and WRITE

LOGIC

Data-In REG.

CLK

OUTPUT

REGISTERS

and LOGIC

256Kx36/

512Kx18

MEMORY

ARRAY

DQP

Cypress Semiconductor Corporation

Document #: 38-05096 Rev. *A

•

3901 North First Street

•

San Jose

•

CA 95134 • 408-943-2600

Revised November 12, 2002

CY7C1366B-250BZC相似产品对比

	CY7C1366B-250BZC	CY7C1367B-250BZC	CY7C1366B-250AC	CY7C1366B-250BGC	CY7C1367B-250AC	CY7C1367B-250BGC
描述	Cache SRAM, 256KX36, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165	Cache SRAM, 512KX18, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165	Cache SRAM, 256KX36, 2.6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	Cache SRAM, 256KX36, 2.6ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119	Cache SRAM, 512KX18, 2.6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	Cache SRAM, 512KX18, 2.6ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合
零件包装代码	BGA	BGA	QFP	BGA	QFP	BGA
包装说明	13 X 15 MM, 1.20 MM HEIGHT, FBGA-165	13 X 15 MM, 1.20 MM HEIGHT, FBGA-165	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
针数	165	165	100	119	100	119
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
ECCN代码	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
最长访问时间	2.6 ns	2.6 ns	2.6 ns	2.6 ns	2.6 ns	2.6 ns
其他特性	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)	250 MHz	250 MHz	250 MHz	250 MHz	250 MHz	250 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	R-PBGA-B165	R-PBGA-B165	R-PQFP-G100	R-PBGA-B119	R-PQFP-G100	R-PBGA-B119
长度	15 mm	15 mm	20 mm	22 mm	20 mm	22 mm
内存密度	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit
内存集成电路类型	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM
内存宽度	36	18	36	36	18	18
湿度敏感等级	1	1	1	1	1	1
功能数量	1	1	1	1	1	1
端子数量	165	165	100	119	100	119
字数	262144 words	524288 words	262144 words	262144 words	524288 words	524288 words
字数代码	256000	512000	256000	256000	512000	512000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
组织	256KX36	512KX18	256KX36	256KX36	512KX18	512KX18
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TBGA	TBGA	LQFP	BGA	LQFP	BGA
封装等效代码	BGA165,11X15,40	BGA165,11X15,40	QFP100,.63X.87	BGA119,7X17,50	QFP100,.63X.87	BGA119,7X17,50
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	FLATPACK, LOW PROFILE	GRID ARRAY	FLATPACK, LOW PROFILE	GRID ARRAY
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
峰值回流温度（摄氏度）	225	225	225	225	225	225
电源	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.2 mm	1.2 mm	1.6 mm	2.4 mm	1.6 mm	2.4 mm
最大待机电流	0.03 A	0.03 A	0.03 A	0.03 A	0.03 A	0.03 A
最小待机电流	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V
最大压摆率	0.25 mA	0.25 mA	0.25 mA	0.25 mA	0.25 mA	0.25 mA
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子形式	BALL	BALL	GULL WING	BALL	GULL WING	BALL
端子节距	1 mm	1 mm	0.65 mm	1.27 mm	0.65 mm	1.27 mm
端子位置	BOTTOM	BOTTOM	QUAD	BOTTOM	QUAD	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
宽度	13 mm	13 mm	14 mm	14 mm	14 mm	14 mm
Base Number Matches	1	1	1	1	-	-

CY7C1366B-250BZC

CY7C1366B-250BZC概述

CY7C1366B-250BZC规格参数

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