025/0251
PRELIMINARY
CY7C09079/89/99
CY7C09179/89/99
32K/64K/128K x 8/9
Synchronous Dual-Port Static RAM
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• 6 Flow-Through/Pipelined devices
— 32K x 8/9 organizations (CY7C09079/179)
— 64K x 8/9 organizations (CY7C09089/189)
— 128K x 8/9 organizations (CY7C09099/199)
• 3 Modes
— Flow-Through
— Pipelined
— Burst
• Pipelined output mode on both ports allows fast
100-MHz cycle time
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5/7.5/9/12 ns (max.)
• Low operating power
— Active= 195 mA (typical)
— Standby= 0.05 mA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
•
•
•
•
•
— Supported in Flow-Through and Pipelined modes
Dual Chip Enables for easy depth expansion
Automatic power-down
Commercial and Industrial temperature ranges
Available in 100-pin TQFP
Pin-compatible and functionally equivalent to
IDT709079, IDT70908, and IDT709089
Logic Block Diagram
R/W
L
OE
L
R/W
R
OE
R
CE
0L
CE
1L
1
0/1
1
0/1
0
0
CE
0R
CE
1R
FT/Pipe
L
[1]
0/1
1
0
0
1
0/1
FT/Pipe
R
[1]
8/9
8/9
I/O
0L
–I/O
7/8L
I/O
Control
[2]
I/O
0R
–I/O
7/8R
I/O
Control
15/16/17
[2]
15/16/17
A
0
–A
14/15/16L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
A
0
–A
14/15/16R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
Notes:
1. I/O
0
–I/O
7
for x8 devices; I/O
0
–I/O
8
for x9 devices.
2. A
0
–A
14
for 32K; A
0
–A
15
for 64K; and A
0
–A
16
for 128K devices.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
• 408-943-2600
November 23, 1998
PRELIMINARY
Functional Description
The CY7C09079/89/99 and CY7C09179/89/99 are high
speed synchronous CMOS 32K, 64K, and 128K x 8/9 du-
al-port static RAMs. Two ports are provided, permitting inde-
pendent, simultaneous access for reads and writes to any lo-
cation in memory.
[3]
Registers on control, address, and data
lines allow for minimal set-up and hold times. In pipelined out-
put mode, data is registered for decreased cycle time. Clock
to data valid t
CD2
= 6.5 ns (pipelined). Flow-through mode can
also be used to bypass the pipelined output register to elimi-
nate access latency. In flow-through mode data will be avail-
able t
CD1
= 15 ns after the address is clocked into the device.
Pipelined output or flow-through mode is selected via the
FT/Pipe pin.
Each port contains a burst counter on the input address regis-
ter. The internal write pulse width is independent of the LOW-
to-HIGH transition of the clock signal. The internal write pulse
is self-timed to allow the shortest possible cycle times.
CY7C09079/89/99
CY7C09179/89/99
A HIGH on CE
0
or LOW on CE
1
for one clock cycle will power
down the internal circuitry to reduce the static power consump-
tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelined mode, one cycle is required with CE
0
LOW and CE
1
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s address strobe
(ADS). When the port’s count enable (CNTEN) is asserted, the
address counter will increment on each LOW-to-HIGH transi-
tion of that port’s clock signal. This will read/write one word
from/into each successive address location until CNTEN is
deasserted. The counter can address the entire memory array
and will loop back to the start. Counter reset (CNTRST) is used
to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Note:
3. When writing simultaneously to the same location, the final value cannot be guaranteed.
2
PRELIMINARY
CY7C09079/89/99
CY7C09179/89/99
Pin Configurations
100-Pin TQFP
(Top View)
CNTENR
CNTENL
ADSR
CLKR
ADSL
CLKL
GND
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A6L
A5L
A4L
A3L
A2L
A1L
A0L
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
A7L
A8L
A9L
A10L
A11L
A12L
A13L
A14L
[Note 4] A15L
[Note 5] A16L
VCC
NC
NC
NC
NC
CE0L
CE1L
CNTRSTL
R/WL
OEL
[Note 6] FT/PIPEL
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75
74
73
72
71
70
69
68
67
66
NC
NC
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R [Note 4]
A16R [Note 5]
GND
NC
NC
NC
NC
CE0R
CE1R
CNTRSTR
R/WR
OER
FT/PIPER [Note 6]
GND
NC
CY7C09099 (128K x 8)
CY7C09089 (64K x 8)
CY7C09079 (32K x 8)
NC
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/01R
GND
NC
GND
GND
NC
VCC
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
Notes:
4. This pin is NC for CY7C09079.
5. This pin is NC for CY7C09079 and CY7C09089.
6. For CY7C09079 and CY7C09089, pin #23 connected to V
CC
is equivalent to an IDT x8 pipelined device; connecting pin #23 and #53 to GND is equivalent to
an IDT x8 flow-through device.
I/O0L
3
VCC
NC
PRELIMINARY
CY7C09079/89/99
CY7C09179/89/99
Pin Configurations
(continued)
100-Pin TQFP
(Top View)
CNTENR
CNTENL
ADSR
CLKR
ADSL
CLKL
GND
GND
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A6L
A5L
A4L
A3L
A2L
A1L
A0L
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
A7L
A8L
A9L
A10L
A11L
A12L
A13L
A14L
[Note 7] A15L
[Note 8] A16L
VCC
NC
NC
NC
NC
CE0L
CE1L
CNTRSTL
R/WL
OEL
FT/PIPEL
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75
74
73
72
71
70
69
68
67
66
NC
NC
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R [Note 7]
A16R [Note 8]
GND
NC
NC
NC
NC
CE0R
CE1R
CNTRSTR
R/WR
OER
FT/PIPER
GND
NC
CY7C09199 (128K x 9)
CY7C09189 (64K x 9)
CY7C09179 (32K x 9)
NC
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
GND
GND
VCC
GND
VCC
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
Selection Guide
CY7C09079/89/99
CY7C09179/89/99
-6
f
MAX2
(MHz) (Pipelined)
Max Access Time (ns) (Clock to Data,
Pipelined)
Typical Operating Current I
CC
(mA)
Typical Standby Current for I
SB1
(mA)
(Both ports TTL Level)
Typical Standby Current for I
SB3
(mA)
(Both ports CMOS level)
Notes:
7. This pin is NC for CY7C09179.
8. This pin is NC for CY7C09179 and CY7C09189.
I/O0L
CY7C09079/89/99
CY7C09179/89/99
-7
83
7.5
235
40
0.05
I/01R
CY7C09079/89/99
CY7C09179/89/99
-9
67
9
215
35
0.05
NC
CY7C09079/89/99
CY7C09179/89/99
-12
50
12
195
30
0.05
100
6.5
250
45
0.05
4
PRELIMINARY
Pin Definitions
Left Port
A
0L
–A
16L
ADS
L
Right Port
A
0R
–A
16R
ADS
R
Description
CY7C09079/89/99
CY7C09179/89/99
Address Inputs (A
0
−A
14
for 32K; A
0
−A
15
for 64K; and A
0
−A
16
for 128K devices).
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads the
burst counter with the address present on the address pins.
Chip Enable Input. To select either the left or right port, both CE
0
AND CE
1
must be asserted to
their active states (CE
0
≤
V
IL
and CE
1
≥
V
IH
).
Clock Signal. This input can be free running or strobed. Maximum clock input rate is f
MAX
.
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data Bus Input/Output (I/O
0
–I/O
7
for x8 devices; I/O
0
–I/O
8
for x9 devices).
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For
read operations, assert this pin HIGH.
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
Ground Input.
No Connect.
Power Input.
Static Discharge Voltage ........................................... >1100V
Latch-Up Current...................................................... >200mA
CE
0L
,CE
1L
CLK
L
CNTEN
L
CE
0R
,CE
1R
CLK
R
CNTEN
R
CNTRST
L
I/O
0L
–I/O
8L
OE
L
R/W
L
FT/PIPE
L
GND
NC
V
CC
CNTRST
R
I/O
0R
–I/O
8R
OE
R
R/W
R
FT/PIPE
R
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65
°
C to +150
°
C
Ambient Temperature with Power Applied ..–55
°
C to +125
°
C
Supply Voltage to Ground Potential ............... –0.3V to +7.0V
DC Voltage Applied to
Outputs in High Z State ................................. –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
Output Current into Outputs (LOW) .............................20 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0
°
C to +70
°
C
−40
°
C to +85
°
C
V
CC
5V
±
10%
5V
±
10%
Shaded area contains advance information.
5
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