The PLLs incorporated in all Delta39K CPLDs are Spread
Aware. This feature refers to the ability of the PLL to track a
spread-spectrum input clock such that its spread is seen on
the output clock. Spread-spectrum is a method of 'spreading'
or modulating a fundamental or original frequency in a con-
trolled, oscillatory manner, such that the electromagnetic en-
ergy broadcast at any given component in the frequency
spectrum is below the maximum value imposed by FCC reg-
ulations. Spread Aware does not mean that the PLL is capa-
ble of generating a spread-spectrum output from a non
spread-spectrum input.
When configured with a x1, x2 or x4 multiply option the
Delta39K PLL is Spread Aware whereas the x8 multiply op-
tion does not support the Spread Aware feature.
Designers may choose to use the spread aware Delta39K
PLL with a spread spectrum input clock. Down spread, up
spread, or some form of middle spread such as center spread
may be used on the incoming clock. However, the total
amount of spread in either or both directions should be limited
to 0.6% of the fundamental frequency. The modulation fre-
quency of the spread should be 50 kHz or less in order to
ensure that the PLL will meet the performance specified in the
data sheet and maintain its intended 1 MHz loop bandwidth.
Value
N/A
12.5- 33 100-266 1-6,8,16 6.25-266 3.125-133
25-66
50-133
100-266 1-6,8,16 6.25-266 3.125-133
100-266 1-6,8,16 6.25-266 3.125-133
3.125-66
66-f
MAX
Lock Detection
A finite amount of time is required from the moment that the
incoming clock signal is placed on the GCLK[0] pin, and thus
drives the source of the PLL, to the time that the PLL actually
achieves steady-state operation, or lock. Designs that contain
logic that will not operate properly until a valid clock signal is
present at the output of the PLL, are dependent upon the PLL
first achieving lock. Designs such as these may require a sig-
nal to indicate when the PLL has reached lock. The PLL can
be configured to generate a lock detect signal at a dedicated
I/O pin. This pin is fed by a multiplexor that can be configured
to select either a general-purpose I/O function or a lock de-
tection indicator function for this pin.
100-133 100-133 1-6,8,16 6.25-133
133-f
MAX
N/A
N/A
133-f
MAX
Notes:
2. An off-chip clock is the output of a toggle flip-flop, which acts as a /2.
3. When an off-chip clock is fed back to ext_fdbk, the toggle flip-flop is effectively placed into the feedback path, resulting in an implicit x2 on top of the x1 multiplication
setting.
3
Delta39K PLL and Clock Tree
JTAG Support
The Delta39K PLL supports the JTAG instruction INTEST.
When the Delta39K device is in JTAG mode and is executing
the instruction INTEST, the clock driving the TCK pin is mul-
tiplexed onto INTCLK[3:0]. This allows the internal logic to be
controlled by the JTAG clock, TCK, instead of the system
clock, and enables the user to verify proper operation of his
or her design in a given device. For more information about
JTAG programming, please refer to the application note titled
'Using IEEE 1149.1 Boundary Scan (JTAG) With Cypress
Ultra37000 CPLDs,' which can be downloaded from ht-
tp://www.cypress.com/pld/pldappnotes.html.
module off_chip_example(clkin, offchipclock);
input clkin;
output offchipclock;
wire plloutclock;
reg offchipclock;
assign plloutclock = clkin;
always@ (posedge plloutclock)
begin
if (plloutclock)
offchipclock <= ~( offchipclock);
end
endmodule
Listing 1b: Verilog Example of Off-chip Clock
Multiple identical output clocks can be buffered from a single
global clock by driving multiple outputs or 'copies' to the same
output described, above.
Off-Chip Clocking and Buffering
The Delta39K global clocks, INTCLK[3:0], may be driven
off-chip by clocking a macrocell or I/O register configured as
a toggle flip-flop (TFF). This way, upon every rising edge of
the INTCLK clock used, the register output level will toggle
from its current state (HIGH or LOW) to the opposite state
(LOW or HIGH). Since, for every two rising edges of the IN-
TCLK clock used a single rising edge at the register output is
generated, a periodic signal that is half the frequency of the
register's clock will result. In order to illustrate how to imple-
ment off-chip clocks in source code, sample code in both
VHDL and Verilog is listed below:
library ieee;
use ieee.std_logic_1164.all;
entity off_chip_example is
port (
clkin:
offchipclk: buffer
);
end off_chip_example;
architecture off_chip_arch of off_chip_example is
signal
begin
plloutclock<=clkin;
p1: process (plloutclock)
begin
if (plloutclock'event and plloutclock= '1') then
offchipclock <= not(offchipclock);
end if;
end process;
end off_chip_arch;
Listing 1a: VHDL Example of Off-chip Clock
shifted_clock: std_logic;
in
std_logic;
std_logic
Overview of Software Support
The Delta39K PLL can be configured in either VHDL or Ver-
ilog code using
Warp
Enterprise™,
Warp
Professional™, or
Warp®
Release 6.0 or later software. The methodology for
implementing this configuration is via a component, module,
or LPM instantiation. Since Delta39K contains a single PLL,
each design project should contain only one instantiation of
the PLL.
Selecting a Target Device
When creating a new project or editing a current project to
target a device, only 2.5V/3.3V devices in the Delta39K family
should be selected if PLL functionality is desired. These de-
vices are indicated by a 'V' in the package name, while low
voltage device selections include a “Z” in the package name
and do not offer PLL functionality. An example of such a de-
vice selection is “CY39100V676-125MBC”.
Component / Module or LPM Instantiation
The PLL configuration may be implemented by instantiating
the PLL component “cy_c39kpll.” For
Warp
to recognize
these instantiations, the user must place the appropriate
VHDL 'library' and 'use' statements or Verilog ‘include’ state-
ments in the source code file where the PLL instantiation re-
sides. For an example of the PLL instantiation in source code,
please see Listing 2a and 2b. In these samples, 'clkin' is mul-
tiplied by 4, while clock signals 'm1p0clock', 'm2p45clock',
'm4p0clock', and 'm4p90clock' are internal clocks accessible
to every register on the selected Delta39K device. Each of the
four internal clocks is configured with different divide and
phase shift selections. 'm1p0clock' is also configured to tog-
gle 'off chip clock' as an off-chip clock. The method of feed-
back selected is 'DIRECT'.
library ieee;
use ieee.std_logic_1164.all;
4
Delta39K PLL and Clock Tree
end pll_arch;
library cypress;
use cypress.lpmpkg.all;
use cypress.rtlpkg.all;
entity pll_example is
port (
clkin:
offchipclock:
);
end pll_example;
architecture pll_arch of pll_example is
signal
begin
defparam U0.feedback = `DIRECT; // optional
U0: cy_c39kpll
generic map(
feedback
multiply
gclk0_phase
gclk1_phase
gclk2_phase
gclk3_phase
)
port map(
pll_in
ext_fdbk
gclk0
gclk1
gclk2
gclk3
);
p0: process (m1p0clock)
begin
if (m1p0clock'event and m1p0clock = '1') then
offchipclock <= not(offchipclock);
end if;
end process;
=> clkin,
=> zero,-- optional
=> m1p0clock,-- optional
=> open,-- optional
=> open, -- optional
=> open -- optional
always @(posedge m1p0clock)
begin
offchipclock = ~(offchipclock);
end
endmodule
Listing 2b: Verilog Sample of PLL Instantiation
The PLL instantiation can be pasted into the source code by
selecting “CY 39kPLL” from the “Template” pull-down on the
toolbar. The text of the PLL instantiation will be automatically
inserted directly at the last cursor position in the source code
displayed in the editor window. There will be default values
listed for some of the instantiation items, but those that are
either blank or require modification must be typed in manually
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