Datasheet> 器件分类 > 可编程逻辑器件> 可编程逻辑> A32140DX-1PQ208CX79

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A32140DX-1PQ208CX79: 产品描述Field Programmable Gate Array, 1866-Cell, CMOS, PQFP208,; 产品类别可编程逻辑器件可编程逻辑; 文件大小2MB，共84页; 制造商Actel; 官网地址http://www.actel.com/; 标准

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A32140DX-1PQ208CX79概述

Field Programmable Gate Array, 1866-Cell, CMOS, PQFP208,

A32140DX-1PQ208CX79规格参数

参数名称	属性值
是否Rohs认证	符合
Reach Compliance Code	unknown
JESD-30 代码	S-PQFP-G208
湿度敏感等级	3
输入次数	176
逻辑单元数量	1866
输出次数	176
端子数量	208
最高工作温度	70 °C
最低工作温度
封装主体材料	PLASTIC/EPOXY
封装代码	QFP
封装等效代码	QFP208,1.2SQ,20
封装形状	SQUARE
封装形式	FLATPACK
电源	5 V
可编程逻辑类型	FIELD PROGRAMMABLE GATE ARRAY
认证状态	Not Qualified
标称供电电压	5 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子形式	GULL WING
端子节距	0.5 mm
端子位置	QUAD
Base Number Matches	1

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v3.0

Integrator Series FPGAs:

1200XL and 3200DX Families

Fe a t ur es

High C apaci t y

G en er al D e sc r i p t i on

•

2,500 to 30,000 Logic Gates

Up to 3Kbits Configurable Dual-Port SRAM

Fast Wide-Decode Circuitry

Up to 250 User-Programmable I/O Pins

225 MHz Performance

5 ns Dual-Port SRAM Access

100 MHz FIFOs

7.5 ns 35-Bit Address Decode

High P er f or m ance

Actel’s Integrator Series FPGAs are the first programmable

logic devices optimized for high-speed system logic

integration. Based on Actel’s proprietary antifuse

technology and 0.6-micron double metal CMOS process,

Integrator Series devices offer a fine-grained, register-rich

architecture with embedded dual-port SRAM and

wide-decode circuitry.

Integrator Series’ 3200DX and 1200XL families were

designed to integrate system logic which is typically

implemented in multiple CPLDs, PALs, and FPGAs. These

devices provide the features and performance required for

today’s complex, high-speed digital logic systems. The

3200DX family offers fast dual-port SRAM for implementing

FIFOs, LIFOs, and temporary data storage. The large

number of storage elements can efficiently address

applications requiring wide datapath manipulation and

transformation functions such as telecommunications,

networking, and DSP.

E ase -of- Int egr at ion

• Synthesis-Friendly Architecture Supports ASIC Design

Methodologies.

• 95–100% Device Utilization using Automatic

Place-and-Route Tools.

• Deterministic, User-Controllable Timing Via Timing

Driven Software Tools with Up To 100% Pin Fixing.

• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing.

I n t eg r a t o r Se r i e s P r o du c t P r of i l e F am i l y

1200XL

Device

A1225XL

2,500

N/A

231

220

N/A

231

A1240XL

4,000

N/A

348

336

N/A

348

104

A1280XL

8,000

N/A

624

608

N/A

624

140

3200DX

A3265DX

6,500

N/A

510

475

N/A

510

126

PL84

PQ100

PQ160

TQ176

A32100DX

10,000

2,048

700

662

700

152

Yes

PL84

PQ160

PQ208

TQ176

CQ84

A32140DX

14,000

N/A

954

912

N/A

954

176

Yes

PL84

PQ160

PQ208

TQ176

CQ256

A32200DX

20,000

2,560

1,230

1,184

1,230

202

Yes

PQ208

RQ208

RQ240

CQ208

CQ256

A32300DX

30,000

3,072

1,888

1,833

1,888

250

Yes

RQ208

RQ240

CQ256

Capacity

Logic Gates

SRAM Bits

Sequential

Combinatorial

Decode

Logic Modules

SRAM Modules

(64x4 or 32x8)

Dedicated Flip-Flops

Clocks

User I/O

(Maximum)

JTAG

Packages

PL84

PQ100

VQ100

PG100

PL84 PQ100

PQ144

TQ176

PG132

PL84

PQ160 PQ208

TQ176

PG176 CQ172

Note:

Logic gate capacity does not include SRAM bits as logic.

F eb r u a r y 2 0 0 1

A32140DX-1PQ208CX79

A32140DX-1PQ208CX79概述

A32140DX-1PQ208CX79规格参数

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