Revision 12
ProASIC3 Flash Family FPGAs
with Optional Soft ARM Support
Features and Benefits
High Capacity
• 15 k to 1 M System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X
†
and LVCMOS
2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os
‡
• Programmable Output Slew Rate
†
and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities
and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
†
• True Dual-Port SRAM (except ×18)
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI
†
In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption (except ARM
®
-enabled ProASIC
®
3 devices)
via JTAG (IEEE 1532–compliant)
†
• FlashLock
®
to Secure FPGA Contents
Clock Conditioning Circuit (CCC) and PLL
†
Low Power
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
Embedded Memory
†
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
ARM Processor Support in ProASIC3 FPGAs
ProASIC3 Devices
Cortex-M1 Devices
2
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
RAM Kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Kbits
Secure (AES) ISP
3
Integrated PLL in CCCs
VersaNet Globals
4
I/O Banks
Maximum User I/Os
Package Pins
QFN
CS
VQFP
TQFP
PQFP
FBGA
A3P015
1
15,000
128
384
–
–
1
–
–
6
2
49
QN68
A3P030
30,000
256
768
–
–
1
–
–
6
2
81
QN48, QN68,
QN132
VQ100
A3P060
60,000
512
1,536
18
4
1
Yes
1
18
2
96
QN132
CS121
VQ100
TQ144
FG144
A3P125
125,000
1,024
3,072
36
8
1
Yes
1
18
2
133
QN132
VQ100
TQ144
PQ208
FG144
A3P250
M1A3P250
250,000
2,048
6,144
36
8
1
Yes
1
18
4
157
QN132
5
VQ100
PQ208
PQ208
FG144/256
5
FG144/256/
484
PQ208
FG144/256/
484
A3P400
M1A3P400
400,000
–
9,216
54
12
1
Yes
1
18
4
194
A3P600
M1A3P600
600,000
–
13,824
108
24
1
Yes
1
18
4
235
• M1 ProASIC3 Devices—ARM
®
Cortex™-M1 Soft Processor
Available with or without Debug
A3P1000
M1A3P1000
1,000,000
–
24,576
144
32
1
Yes
1
18
4
300
PQ208
FG144/256/
484
Notes:
1. A3P015 is not recommended for new designs.
2. Refer to the
Cortex-M1
product brief for more information.
3. AES is not available for Cortex-M1 ProASIC3 devices.
4. Six chip (main) and three quadrant global networks are available for A3P060 and above.
5. The M1A3P250 device does not support this package.
6. For higher densities and support of additional features, refer to the
ProASIC3E Flash Family FPGAs
datasheet.
† A3P015 and A3P030 devices do not support this feature.
September 2012
© 2012 Microsemi Corporation
‡ Supported only by A3P015 and A3P030 devices.
I
ProASIC3 Flash Family FPGAs
I/Os Per Package
1
ProASIC3
Devices
Cortex-M1
Devices
A3P015
2
A3P030
A3P060
A3P125
A3P250
3
M1A3P250
3,5
I/O Type
Differential I/O Pairs
Differential I/O Pairs
Differential I/O Pairs
Differential I/O Pairs
–
–
–
–
–
–
35
25
44
74
FG484
23 × 23
529
1.0
2.23
Single-Ended I/O
4
Single-Ended I/O
4
Single-Ended I/O
4
Single-Ended I/O
4
–
–
–
–
–
–
154
97
177
300
289
1.0
1.60
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
A3P400
3
M1A3P400
3
A3P600
M1A3P600
A3P1000
M1A3P1000
Package
QN48
QN68
QN132
5
CS121
VQ100
TQ144
PQ208
FG144
FG256
5,6
FG484
6
–
49
–
–
–
–
–
–
–
–
34
49
81
–
77
–
–
–
–
–
–
–
80
96
71
91
–
96
–
–
–
–
84
–
71
100
133
97
–
–
–
–
87
–
68
–
151
97
157
–
–
–
19
–
13
–
34
24
38
–
–
–
–
–
–
151
97
178
194
–
–
–
–
–
–
34
25
38
38
–
–
–
–
–
–
–
–
154
97
177
235
–
35
25
43
60
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the
ProASIC3 FPGA Fabric User’s Guide
to ensure complying with design and board migration requirements.
2. A3P015 is not recommended for new designs.
3. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer to
the
ProASIC3 FPGA Fabric User’s Guide
for position assignments of the 15 LVPECL pairs.
4. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
5. The M1A3P250 device does not support FG256 or QN132 packages.
6. FG256 and FG484 are footprint-compatible packages.
Table 1 • ProASIC3 FPGAs Package Sizes Dimensions
Package
Length × Width
(mm\mm)
Nominal Area
(mm
2
)
Pitch (mm)
Height (mm)
CS121
6×6
36
0.5
0.99
QN48
6×6
36
0.4
0.90
QN68
8×8
64
0.4
0.90
QN132
8×8
64
0.5
0.75
VQ100
14 × 14
196
0.5
1.00
TQ144
20 × 20
400
0.5
1.40
PQ208
28 × 28
784
0.5
3.40
FG144
13 × 13
169
1.0
1.45
FG256
17 × 17
II
R evis i o n 12
ProASIC3 Flash Family FPGAs
ProASIC3 Ordering Information
.
A3P1000
_
1
FG
G
144
Y
I
Application (Temperature Range)
Blank = Commercial (0°C to +70°C Ambient Temperature)
I = Industrial (
–
40°C to +85°C Ambient Temperature)
PP = Pre-Production
ES = Engineering Sample (Room Temperature Only)
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G= RoHS-Compliant (Green) Packaging (some packages also halogen-free)
Package Type
QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches)
VQ = Very Thin Quad Flat Pack (0.5 mm pitch)
TQ = Thin Quad Flat Pack (0.5 mm pitch)
PQ = Plastic Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
CS = Chip Scale Package (0.5 mm pitch)
Speed Grade
Blank = Standard
1 = 15% Faster than Standard
2 = 25% Faster than Standard
Part Number
ProASIC3 Devices
A3P015 =
A3P030 =
A3P060 =
A3P125 =
A3P250 =
A3P400 =
A3P600 =
A3P1000 =
15,000 System Gates (A3P015 is not recommended for new designs.)
30,000 System Gates
60,000 System Gates
125,000 System Gates
250,000 System Gates
400,000 System Gates
600,000 System Gates
1,000,000 System Gates
ProASIC3 Devices with Cortex-M1
M1A3P250 =
M1A3P400 =
M1A3P600 =
M1A3P1000 =
250,000 System Gates
400,000 System Gates
600,000 System Gates
1,000,000 System Gates
ProASIC3 Device Status
ProASIC3 Devices
A3P015
A3P030
A3P060
A3P125
A3P250
A3P400
A3P600
A3P1000
Status
Not recommended for new designs.
Production
Production
Production
Production
Production
Production
Production
M1A3P250
M1A3P400
M1A3P600
M1A3P1000
Production
Production
Production
Production
Cortex-M1 Devices
Status
R ev i si o n 1 2
III
ProASIC3 Flash Family FPGAs
Temperature Grade Offerings
Package
Cortex-M1 Devices
QN48
QN68
QN132
CS121
VQ100
TQ144
PQ208
FG144
FG256
FG484
–
C, I
–
–
–
–
–
–
–
–
C, I
C, I
C, I
–
C, I
–
–
–
–
–
–
–
C, I
C, I
C, I
C, I
–
C, I
–
–
–
–
C, I
–
C, I
C, I
C, I
C, I
–
–
A3P015
*
A3P030
A3P060
A3P125
A3P250
M1A3P250
–
–
C, I
–
C, I
–
C, I
C, I
C, I
–
A3P400
M1A3P400
–
–
–
–
–
–
C, I
C, I
C, I
C, I
A3P600
M1A3P600
–
–
–
–
–
–
C, I
C, I
C, I
C, I
A3P1000
M1A3P1000
–
–
–
–
–
–
C, I
C, I
C, I
C, I
Note:
*A3P015 is not recommended for new designs.
C = Commercial temperature range: 0°C to 70°C ambient temperature
I = Industrial temperature range: –40°C to 85°C ambient temperature
Speed Grade and Temperature Grade Matrix
Temperature Grade
C
1
I
2
Std.
–1
–2
Notes:
1. C = Commercial temperature range: 0°C to 70°C ambient temperature
2. I = Industrial temperature range: –40°C to 85°C ambient temperature
References made to ProASIC3 devices also apply to ARM-enabled ProASIC3 devices. The ARM-enabled part numbers start with
M1 (Cortex-M1).
Contact your local Microsemi representative for device availability:
http://www.microsemi.com/soc/contact/default.aspx.
A3P015 and A3P030
The A3P015 and A3P030 are architecturally compatible; there are no RAM or PLL features.
Devices Not Recommended For New Designs
A3P015 is not recommended for new designs.
IV
R evis i o n 12
ProASIC3 Flash Family FPGAs
Table of Contents
ProASIC3 Device Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
ProASIC3 DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-83
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-92
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-94
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-110
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-111
Pin Descriptions
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-2
3-3
3-4
3-4
Package Pin Assignments
QN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
QN68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
QN132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
CS121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
TQ144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
FG144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52
FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
R ev i si o n 1 2
V
FPGA/CPLD
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