Philips Semiconductors
Product specification
TrenchMOS™ transistor
Standard level FET
GENERAL DESCRIPTION
N-channel enhancement mode
standard level field-effect power
transistor in a plastic envelope
suitable for surface mounting using
’trench’ technology. The device
features very low on-state resistance
and has integral zener diodes giving
ESD protection up to 2kV. It is
intended for use in automotive and
general
purpose
switching
applications.
BUK7656-30
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
V
GS
= 10 V
MAX.
30
24
60
175
56
UNIT
V
A
W
˚C
mΩ
PINNING - SOT404
PIN
1
2
3
mb
gate
drain
source
drain
DESCRIPTION
PIN CONFIGURATION
mb
SYMBOL
d
g
2
1
3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±V
GS
I
D
I
D
I
DM
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 kΩ
-
T
mb
= 25 ˚C
T
mb
= 100 ˚C
T
mb
= 25 ˚C
T
mb
= 25 ˚C
-
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
20
24
20
96
60
175
UNIT
V
V
V
A
A
A
W
˚C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
pcb mounted, minimum
footprint
TYP.
-
50
MAX.
2.5
-
UNIT
K/W
K/W
ESD LIMITING VALUE
SYMBOL
V
C
PARAMETER
Electrostatic discharge capacitor
voltage, all pins
CONDITIONS
Human body model
(100 pF, 1.5 kΩ)
MIN.
-
MAX.
2
UNIT
kV
June 1997
1
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Standard level FET
STATIC CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
V
(BR)DSS
V
GS(TO)
I
DSS
I
GSS
±V
(BR)GSS
R
DS(ON)
PARAMETER
Drain-source breakdown
voltage
Gate threshold voltage
Zero gate voltage drain current
Gate source leakage current
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175˚C
T
j
= -55˚C
V
DS
= 30 V; V
GS
= 0 V;
V
GS
=
±10
V; V
DS
= 0 V
T
j
= 175˚C
T
j
= 175˚C
MIN.
30
27
2.0
1.0
-
-
-
-
-
16
-
-
TYP.
-
-
3.0
-
-
0.05
-
0.02
-
-
50
-
BUK7656-30
MAX.
-
-
4.0
-
4.4
10
500
1
20
-
56
104
UNIT
V
V
V
V
V
µA
µA
µA
µA
V
mΩ
mΩ
Gate source breakdown voltage I
G
=
±1
mA;
Drain-source on-state
V
GS
= 10 V; I
D
= 25 A
resistance
V
GS
= 10 V; I
D
= 12 A; T
j
= 175˚C
DYNAMIC CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
g
fs
Q
g(tot)
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d on
t
r
t
d off
t
f
L
d
L
d
L
s
PARAMETER
Forward transconductance
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Input capacitance
Output capacitance
Feedback capacitance
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal drain inductance
Internal source inductance
CONDITIONS
V
DS
= 25 V; I
D
= 12 A
I
D
= 10 A; V
DD
= 30 V; V
GS
= 10 V
MIN.
2
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP.
7.2
13
3.2
5.4
385
152
85
9
40
15
20
3.5
4.5
7.5
MAX.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UNIT
S
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
nH
nH
nH
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
V
DD
= 30 V; I
D
= 25 A;
V
GS
= 10 V; R
G
= 10
Ω
Resistive load
Measured from contact screw on
tab to centre of die
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
I
DR
I
DRM
V
SD
t
rr
Q
rr
PARAMETER
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
-
I
F
= 25 A; V
GS
= 0 V
I
F
= 25 A; -dI
F
/dt = 100 A/µs;
V
GS
= 0 V; V
R
= 25 V
-
-
-
-
TYP.
-
-
0.99
154
0.5
MAX.
24
96
1.2
-
-
UNIT
A
A
V
ns
µC
June 1997
2
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Standard level FET
AVALANCHE LIMITING VALUE
SYMBOL
W
DSS
PARAMETER
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I
D
= 12 A; V
DD
≤
25 V;
V
GS
= 10 V; R
GS
= 50
Ω;
T
mb
= 25 ˚C
MIN.
-
TYP.
-
BUK7656-30
MAX.
15
UNIT
mJ
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
100
ID, Drain current (Amps)
/
DS
=V
ID
PHP24N03T
RD
O
S(
N)
10 us
100 us
10
DC
1 ms
10 ms
Tmb = 25 C
0
20
40
60
80 100
Tmb / C
120
140
160
180
1
1
10
VDS, Drain-source voltage (Volts)
100
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
Normalised Current Derating
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Transient thermal impedance, Zth j-mb (K/W) PHP24N03T
120
110
100
90
80
70
60
50
40
30
20
10
0
ID%
10
D=
1
0.5
0.2
0.1
0.05
0.1
0.02
P
D
t
p
D=
t
p
T
t
0
T
0.01
0
20
40
60
80 100
Tmb / C
120
140
160
180
1us
10us 100us 1ms 10ms
pulse width, tp (s)
0.1s
1s
10s
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
10 V
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
June 1997
3
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Standard level FET
BUK7656-30
20
ID, Drain current (Amps)
10 V
20 V
PHP24N03T
6.5 V
Tj = 25 C
6V
10
Transconductance, gfs (S)
VDS = 30 V
PHP24N03T
8
Tj = 25 C
6
15
10
5.5 V
5V
5
4.5 V
VGS = 4 V
0
0
5
10
15
20
VDS, Drain-Source voltage (Volts)
25
30
4
175 C
2
0
0
5
10
Drain current, ID (A)
15
20
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
RDS(on), Drain-Source on resistance (Ohms)
VGS = 4 V
4.5 V
5V
PHP24N03T
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
)
a
2
0.2
30V TrenchMOS
5.5 V
0.15
1.5
0.1
1
Tj = 25 C
0.05
10 V
20 V
0.5
0
0
5
10
15
ID, Drain current (Amps)
20
0
-100
-50
0
50
Tj / C
100
150
200
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
Drain current, ID (A)
VDS = 30 V
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 12 A; V
GS
= 10 V
VGS(TO) / V
max.
4
BUK759-60
15
PHP24N03T
5
10
typ.
3
min.
2
5
175 C
Tj = 25 C
1
0
0
2
4
6
Gate-source voltage, VGS (V)
8
10
0
-100
-50
0
50
Tj / C
100
150
200
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
); parameter T
j
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
June 1997
4
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Standard level FET
BUK7656-30
1E-01
Sub-Threshold Conduction
20
Source-Drain diode current, IF(A)
VGS = 0 V
PHP24N03T
1E-02
2%
typ
98%
15
1E-03
10
175 C
Tj = 25 C
1E-04
5
1E-05
0
1E-06
0
0.2
0
1
2
3
4
5
0.4
0.6
0.8
1
Source-Drain voltage, VSDS (V)
1.2
1.4
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Capacitances, Ciss, Coss, Crss (pF)
PHP24N03T
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); parameter T
j
WDSS%
1000
120
110
100
Ciss
90
80
70
60
50
40
30
20
10
0
Coss
100
Crss
10
1
10
Drain-source voltage, VDS (V)
100
20
40
60
80
100
120
Tmb / C
140
160
180
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
)
20
VGS, Gate-Source voltage (Volts)
VDD = 30 V
ID = 10 A
Tj = 25 C
PHP24N03T
+
L
VDS
VDD
15
10
VGS
0
T.U.T.
-
-ID/100
5
RGS
0
R 01
shunt
0
5
10
15
Qg, Gate charge (nC)
20
25
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); parameter V
DS
Fig.16. Avalanche energy test circuit.
2
W
DSS
=
0.5
⋅
LI
D
⋅
BV
DSS
/(BV
DSS
−
V
DD
)
June 1997
5
Rev 1.000
DSP 与 ARM 处理器
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