74ALVCH16374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold
September 2001
Revised September 2001
74ALVCH16374
Low Voltage 16-Bit D-Type Flip-Flop with Bushold
General Description
The ALVCH16374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and output enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
The ALVCH16374 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The 74ALVCH16374 is designed for low voltage (1.65V to
3.6V) V
CC
applications with output compatibility up to 3.6V.
The 74ALVCH16374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
1.65V–3.6V V
CC
supply operation
s
3.6V tolerant control inputs and outputs
s
Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s
t
PD
4.2 ns max for 3.0V to 3.6V V
CC
5.3 ns max for 2.3V to 2.7V V
CC
7.8 ns max for 1.65V to 1.95V V
CC
s
Uses patented noise/EMI reduction circuitry
s
Latch-up conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Order Number
74ALVCH16374GX
(Note 1)
74ALVCH16374MTD
(Note 2)
Package
Number
BGA54A
(Preliminary)
MTD48
Package Descriptions
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1:
BGA package available in Tape and Reel only.
Note 2:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation
DS500627
www.fairchildsemi.com
74ALVCH16374
Connection Diagrams
Pin Assignment for TSSOP
Pin Descriptions
Pin Names
OE
n
CP
n
I
0
–I
15
O
0
–O
15
NC
Description
Output Enable Input (Active LOW)
Clock Pulse Input
Bushold Inputs
Outputs
No Connect
FBGA Pin Assignments
1
A
B
C
D
E
F
G
H
J
O
0
O
2
O
4
O
6
O
8
O
10
O
12
O
14
O
15
2
NC
O
1
O
3
O
5
O
7
O
9
O
11
O
13
NC
3
OE
1
NC
V
CC
GND
GND
GND
V
CC
NC
OE
2
4
CP
1
NC
V
CC
GND
GND
GND
V
CC
NC
CP
2
5
NC
I
1
I
3
I
5
I
7
I
9
I
11
I
13
NC
6
I
0
I
2
I
4
I
6
I
8
I
10
I
12
I
14
I
15
Truth Tables
Inputs
Pin Assignment for FBGA
CP
1
Outputs
I
0
–I
7
H
L
X
X
O
0
–O
7
H
L
O
0
Z
Outputs
I
8
–I
15
H
L
X
X
O
8
–O
15
H
L
O
0
Z
OE
1
L
L
L
H
Inputs
CP
2
L
X
L
X
OE
2
L
L
L
H
(Top Thru View)
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial (HIGH or LOW, control inputs may not float)
Z
=
High Impedance
O
0
=
Previous O
0
before HIGH-to-LOW of CP
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2
74ALVCH16374
Functional Description
The 74ALVCH16374 consists of sixteen edge-triggered
flip-flops with individual D-type inputs and 3-STATE true
outputs. The device is byte controlled with each byte func-
tioning identically, but independent of the other. The control
pins can be shorted together to obtain full 16-bit operation.
Each clock has a buffered clock and buffered Output
Enable common to all flip-flops within that byte. The
description which follows applies to each byte. Each
flip-flop will store the state of their individual I inputs that
meet the setup and hold time requirements on the
LOW-to-HIGH Clock (CP
n
) transition. With the Output
Enable (OE
n
) LOW, the contents of the flip-flops are avail-
able at the outputs. When OE
n
is HIGH, the outputs go to
the high impedance state. Operations of the OE
n
input
does not affect the state of the flip-flops.
Logic Diagram
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74ALVCH16374
Absolute Maximum Ratings
(Note 3)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
) (Note 4)
DC Input Diode Current (I
IK
)
V
I
<
0V
DC Output Diode Current (I
OK
)
V
O
<
0V
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
Storage Temperature Range (T
STG
)
−
0.5V to
+
4.6V
−
0.5V to 4.6V
−
0.5V to V
CC
+
0.5V
−
50 mA
−
50 mA
±
50 mA
±
100 mA
−
65
°
C to
+
150
°
C
Recommended Operating
Conditions
(Note 5)
Power Supply
Operating
Input Voltage (V
I
)
Output Voltage (V
O
)
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
∆
t/
∆
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Note 3:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 4:
I
O
Absolute Maximum Rating must be observed.
Note 5:
Floating or unused control inputs must be held HIGH or LOW.
1.65V to 3.6V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level Input Voltage
Conditions
V
CC
(V)
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
V
IL
LOW Level Input Voltage
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
V
OH
HIGH Level Output Voltage
I
OH
=
100
µA
I
OH
= −4
mA
I
OH
= −6
mA
I
OH
= −12
mA
1.65 - 3.6
1.65
2.3
2.3
2.7
3.0
I
OH
= −24
mA
V
OL
LOW Level Output Voltage
I
OL
=
100
µA
I
OL
=
4 mA
I
OL
=
6 mA
I
OL
=
12 mA
I
OL
=
24 mA
I
OH
HIGH Level Output Current
3.0
1.65 - 3.6
1.65
2.3
2.3
2.7
3.0
1.65
2.3
2.7
3.0
I
OL
LOW Level Output Current
1.65
2.3
2.7
3
I
I
I
I(HOLD)
Input Leakage Current
Bushold Input Maximum
Drive Hold Current
0
≤
V
I
≤
3.6V
V
IN
=
0.58V
V
IN
=
1.07V
V
IN
=
0.7V
V
IN
=
1.7V
V
IN
=
0.8V
V
IN
=
2.0V
0
<
V
O
≤
3.6V
3.6
1.65
1.65
2.3
2.3
3.0
3.0
3.6
25
−25
45
−45
75
−75
±500
µA
V
CC
- 0.2
1.2
2.0
1.7
2.2
2.4
2
0.2
0.45
0.4
0.7
0.4
0.55
−4
−12
−12
−24
4
12
12
24
±5.0
µA
mA
mA
V
V
Min
0.65 x V
CC
1.7
2.0
0.35 x V
CC
0.7
0.8
V
V
Max
Units
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4
74ALVCH16374
DC Electrical Characteristics
Symbol
I
OZ
I
CC
∆I
CC
Parameter
3-STATE Output Leakage
Quiescent Supply Current
Increase in I
CC
per Input
(Continued)
V
CC
(V)
3.6
3.6
3 - 3.6
Conditions
0
≤
V
O
≤
3.6V
V
I
=
V
CC
or GND, I
O
=
0
V
IH
=
V
CC
−
0.6V
Min
Max
±10
40
750
Units
µA
µA
µA
AC Electrical Characteristics
T
A
= −40°C
to
+85°C,
R
L
=
500Ω
Symbol
Parameter
C
L
=
50 pF
V
CC
=
3.3V
±
0.3V
Min
f
CLOCK
t
W
t
S
t
H
f
MAX
t
PHL
, t
PLH
t
PZL
, t
PZH
t
PLZ
, t
PHZ
Clock Frequency
Pulse Width
Setup Time
Hold Time
Maximum Clock Frequency
Propagation Delay
Output Enable Time
Output Disable Time
3.3
1.9
0.5
150
1.0
1.0
1.0
4.2
4.8
4.3
Max
150
3.3
2.2
0.5
150
4.9
5.9
4.7
V
CC
=
2.7V
Min
Max
150
3.3
2.1
0.6
150
1.0
1.0
1.0
5.3
6.2
5.3
C
L
=
30 pF
V
CC
=
2.5V
±
0.2V
Min
Max
150
4.0
2.5
1.0
100
1.5
1.5
1.5
7.8
9.2
6.8
V
CC
=
1.8V
±
0.15V
Min
Max
100
MHz
ns
ns
ns
MHz
ns
ns
ns
Units
Capacitance
Symbol
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Parameter
Control
Data
Conditions
V
I
=
0V or V
CC
V
I
=
0V or V
CC
V
I
=
0V or V
CC
Outputs Enabled f
=
10 MHz, C
L
=
50 pF
Outputs Disabled f
=
10 MHz, C
L
=
50 pF
T
A
= +25°C
V
CC
3.3
3.3
3.3
3.3
2.5
3.3
2.5
Typical
3
6
7
30
31
18
16
pF
Units
pF
pF
5
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