74F191 Up/Down Binary Counter with Preset and Ripple Clock
April 1988
Revised July 1999
74F191
Up/Down Binary Counter with Preset and Ripple Clock
General Description
The 74F191 is a reversible modulo-16 binary counter fea-
turing synchronous counting and asynchronous presetting.
The preset feature allows the 74F191 to be used in pro-
grammable dividers. The Count Enable input, the Terminal
Count output and Ripple Clock output make possible a
variety of methods of implementing multistage counters. In
the counting modes, state changes are initiated by the ris-
ing edge of the clock.
Features
s
High-Speed—125 MHz typical count frequency
s
Synchronous counting
s
Asynchronous parallel load
s
Cascadable
Ordering Code:
Order Number
74F191SC
74F191SJ
74F191PC
Package Number
M16A
M16D
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009495
www.fairchildsemi.com
74F191
Unit Loading/Fan Out
Pin Names
CE
CP
P
0
–P
3
PL
U/D
Q
0
–Q
3
RC
TC
Description
Count Enable Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Parallel Data Inputs
Asynchronous Parallel Load Input (Active LOW)
Up/Down Count Control Input
Flip-Flop Outputs
Ripple Clock Output (Active LOW)
Terminal Count Output (Active HIGH)
U.L.
HIGH/LOW
1.0/3.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
50/33.3
50/33.3
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µA/−1.8
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
−1
mA/20 mA
−1
mA/20 mA
−1
mA/20 mA
Functional Description
The 74F191 is a synchronous up/down 4-bit binary
counter. It contains four edge-triggered flip-flops, with inter-
nal gating and steering logic to provide individual preset,
count-up and count-down operations.
Each circuit has an asynchronous parallel load capability
permitting the counter to be preset to any desired number.
When the Parallel Load (PL) input is LOW, information
present on the Parallel Data inputs (P
0
–P
3
) is loaded into
the counter and appears on the Q outputs. This operation
overrides the counting functions, as indicated in the Mode
Select Table.
A HIGH signal on the CE input inhibits counting. When CE
is LOW, internal state changes are initiated synchronously
by the LOW-to-HIGH transition of the clock input. The
direction of counting is determined by the U/D input signal,
as indicated in the Mode Select Table. CE and U/D can be
changed with the clock in either state, provided only that
the recommended setup and hold times are observed.
Two types of outputs are provided as overflow/underflow
indicators. The Terminal Count (TC) output is normally
LOW and goes HIGH when a circuit reaches zero in the
count-down mode or reaches 15 in the count-up mode. The
TC output will then remain HIGH until a state change
occurs, whether by counting or presetting or until U/D is
changed. The TC output should not be used as a clock sig-
nal because it is subject to decoding spikes.
The TC signal is also used internally to enable the Ripple
Clock (RC) output. The RC output is normally HIGH. When
CE is LOW and TC is HIGH, the RC output will go LOW
when the clock next goes LOW and will stay LOW until the
clock goes HIGH again. This feature simplifies the design
of multistage counters, as indicated in Figure 1 and
Figure 2. In Figure 1, each RC output is used as the clock
input for the next higher stage. This configuration is particu-
larly advantageous when the clock source has a limited
drive capability, since it drives only the first stage. To pre-
vent counting in all stages it is only necessary to inhibit the
first stage, since a HIGH signal on CE inhibits the RC out-
put pulse, as indicated in the RC Truth Table. A disadvan-
tage of this configuration, in some applications, is the
timing skew between state changes in the first and last
stages. This represents the cumulative delay of the clock
as it ripples through the preceding stages.
A method of causing state changes to occur simulta-
neously in all stages is shown in Figure 2. All clock inputs
are driven in parallel and the RC outputs propagate the
carry/borrow signals in ripple fashion. In this configuration
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2
the LOW state duration of the clock must be long enough to
allow the negative-going edge of the carry/borrow signal to
ripple through to the last stage before the clock goes HIGH.
There is no such restriction on the HIGH state duration of
the clock, since the RC output of any device goes HIGH
shortly after its CP input goes HIGH.
The configuration shown in Figure 3 avoids ripple delays
and their associated restrictions. The CE input for a given
stage is formed by combining the TC signals from all the
preceding stages. Note that in order to inhibit counting an
enable signal must be included in each carry gate. The
simple inhibit scheme of Figure 1 and Figure 2 doesn't
apply, because the TC output of a given stage is not
affected by its own CE.
Mode Select Table
Inputs
PL
H
H
L
H
CE
L
L
X
H
U/D
L
H
X
X
CP
Count Up
Count Down
Preset (Asyn.)
No Change (Hold)
X
X
Mode
RC Truth Table
Inputs
CE
L
H
X
TC*
H
X
L
Output
CP
X
X
H
H
RC
*TC is generated internally
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
=
LOW Pulse
74F191
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−0.5V
to V
CC
−0.5V
to
+5.5V
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150°C
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to
+70°C
+4.5V
to
+5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
−60
38
4.75
3.75
−0.6
−1.8
I
OS
I
CC
Output Short-Circuit Current
Power Supply Current
−150
55
mA
mA
Max
Max
10% V
CC
5% V
CC
10% V
CC
2.5
2.7
0.5
5.0
7.0
50
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
µA
µA
µA
V
µA
mA
Min
Min
Min
Max
Max
Max
0.0
0.0
Max
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −1
mA
I
OL
=
20 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA,
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V (except CE)
V
IN
=
0.5V (CE)
V
OUT
=
0V
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