E2O0016-39-81
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
¡ Semiconductor
PROGRAMMABLE DMA CONTROLLER
This version: Aug. 1999
MSM82C37B-5RS/GS/VJS
Previous version: Jan. 1998
GENERAL DESCRIPTION
The MSM82C37B-5RS/GS/VJS, DMA (Direct Memory Access) controller is capable of high-
speed data transfer without CPU intervention and is used as a peripheral device in microcomputer
systems. The device features four independent programmable DMA channels.
Due to the use of silicon gate CMOS technology, standby current is 10
mA
(max.), and power
consumption is as low as 10 mA (max.) when a 5 MHz clock is generated.
All items of AC characteristics are compatible with intel 8237A-5.
FEATURES
• Maximum operating frequency of 5 MHz (Vcc = 5 V
±10%)
• High-speed operation at very low power consumption due to silicon gate CMOS technology
• Wide operating temperature range from –40°C to +85°C
• 4-channels independent DMA control
• DMA request masking and programming
• DMA request priority function
• DREQ and DACK input/output logic inversion
• DMA address increment/decrement selection
• Memory-to-Memory Transfers
• Channel extension by cascade connection
• DMA transfer termination by EOP input
• Intel 8237A-5 compatibility
• TTL Compatible
• 40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM82C37B-5RS)
• 44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM82C37B-5VJS)
• 44-pin Plastic QFP (QFP44-P-910-0.80-2K): (Product name: MSM82C37B-5GS-2K)
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¡ Semiconductor
MSM82C37B-5RS/GS/VJS
AC CHARACTERISTICS
DMA (Master) Mode
Symbol
t
AEL
t
AET
t
AFAB
t
AFC
t
AFDB
t
AHR
t
AHS
t
AHW
Item
Delay Time from CLK Falling Edge
up to AEN Leading Edge
Delay Time from CLK Rising Edge
up to AEN Trailing Edge
Delay Time from CLK Rising Edge
up to Address Floating Status
Delay Time from CLK Rising Edge
up to Read/Write Signal Floating Status
Delay Time from CLK Rising Edge
up to Data Bus Floating Status
Address Valid Hold Time
to Read Signal Trailing Edge
Data Valid Hold Time
to ADSTB Trailing Edge
Address Valid Hold Time
to Write Signal Trailing Edge
Delay Time from CLK Falling Edge
up to Active DACK
t
AK
Delay Time from CLK Rising Edge
up to
EOP
Leading Edge
Delay Time from CLK Rising Edge
up to
EOP
Trailing Edge
t
ASM
t
ASS
t
CH
t
CL
t
CY
Time from CLK Rising Edge
up to Address Valid
Data Set-up Time to ADSTB Trailing Edge
Clock High-level Time
Clock Low-level Time
CLK Cycle Time
Min.
—
—
—
—
—
t
CY
– 100
30
t
CY
– 50
—
—
—
—
100
68
68
200
(Ta = –40 to +85°C, V
CC
= 4.5 to 5.5 V)
Comments
Max.
Unit
200
130
90
120
170
—
—
—
170
170
170
170
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
—
—
(Note 3)
(Note 5)
—
—
—
(Note 6)
(Note 6)
—
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