25/0251
CY2411
54-MHz MPEG
Clock Generator with VCXO
2
Features
• Integrated phase-locked loop
• Low-jitter, high-accuracy outputs
• VCXO with analog adjust
• 3.3V Operation
Part Number
CY2411
Outputs
1
Input Frequency Range
13.5-MHz Pullable Crystal per
Cypress Specification
Benefits
Highest Performance PLL tailored for multimedia applications
Meets critical timing requirements in complex system designs
Large ± 150 ppm range, better linearity
Output Frequencies
1 copy of 54 MHz (3.3V)
Logic Block Diagram
13.5 XIN
OSC
XOUT
Q
Pin Configuration
OUTPUT
DIVIDER
Φ
VCO
P
54 MHz
CY2411
8-pin SOIC
XIN
AVDD
VCXO
AVSS
1
2
3
4
8
7
6
5
XOUT
VSS
54 MHz
VDD
VCXO
PLL
AVDD VDD
AVSS
VSS
Cypress Semiconductor Corporation
Document #: 38-07193 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised November 5, 2001
CY2411
Pin Summary
Name
A
VDD
V
DD
AV
SS
V
SS
X
IN
V
CXO
X
OUT[1]
54 MHz
Pin Number Description
2
5
4
7
1
3
8
6
Analog Voltage Supply
Output Voltage Supply
Analog Ground
Output Ground
Reference Crystal Input
Analog Control for V
CXO
Reference Crystal Output
54 MHz clock output
Absolute Maximum Conditions
Parameter
V
DD
T
S
T
J
Description
Supply Voltage
Storage Temperature
[2]
Junction Temperature
Digital Inputs
Digital Outputs referred to V
DD
Electro-Static Discharge
V
SS
– 0.3
V
SS
– 0.3
2
Min.
–0.5
–65
Max.
7.0
100
100
V
DD
+ 0.3
V
DD
+ 0.3
Unit
V
°C
°C
V
V
kV
Recommended Operating Conditions
Parameter
V
DD
T
A
C
LOAD
P
max
f
REF
Description
Operating Voltage
Ambient Temperature
Max Load Capacitance
Max Output Power Dissipation,
8-pin package
Reference Frequency
10
13.5
Min.
3.0
0
Typ.
3.3
Max.
3.6
70
20
150
30
Unit
V
°C
pF
° C/W
MHz
DC Electrical Characteristics
Parameter
I
OH
I
OL
C
IN
I
IZ
Name
Output High Current
Output Low Current
Input Capacitance
Input Leakage Current
V
CXO
Pullability Range
V
CXO
Input Range
V
CXO
Input Bandwidth
Supply Current
Sum of Core and Output Current
–150
0
DC to 200
15
20
5
+150
AV
DD
Description
V
OH
= V
DD
– 0.5, V
DD
= 3.3 V
V
OL
= 0.5, V
DD
= 3.3 V
Min.
12
12
Typ.
24
24
7
Max.
Unit
mA
mA
pF
µA
ppm
V
kHz
mA
f
∆
xo
V
VCXO
f
VBW
I
DD
Notes:
1. Float XOUT if XIN is externally driven.
2. Rated for 10 years.
Document #: 38-07193 Rev. **
Page 2 of 5
CY2411
AC Electrical Characteristics (V
DD
= 3.3V)
Parameter
[3]
DC
t
3
t
4
t
9
t
10
Name
Output Duty Cycle
Rising Edge Slew Rate
Falling Edge Slew Rate
Clock Jitter
PLL Lock Time
Description
Duty Cycle is defined in
Figure 1,
50% of V
DD
Output Clock Rise Time, 20% - 80% of V
DD
Output Clock Fall Time, 80% to 20% of V
DD
Peak to Peak period jitter
Min.
45
0.8
0.8
Typ.
50
1.4
1.4
200
3
Max.
55
Unit
%
V/ns
V/ns
ps
ms
t
1
t
2
t
3
80%
t
4
54 MHz
50%
54 MHz
20%
Figure 1. Duty Cycle Definition; DC = t
2
/t
1
Figure 2. Rise and Fall Time Definitions
Test Circuit
AV
DD
0.1
µ
F
OUTPUTS
CLK out
C
LOAD
V
DD
0.1
µ
F
GND
Ordering Information
Ordering Code
CY2411SC
CY2411SCT
Note:
3. Not 100% tested.
Package
Name
S8
S8
Package Type
8-Pin SOIC
8-Pin SOIC on Tape and Reel
Operating
Range
Commercial
Commercial
3.3V
3.3V
Operating
Voltage
Document #: 38-07193 Rev. **
Page 3 of 5
CY2411
Pin Diagrams
8-Lead (150-Mil) SOIC S8
51-85066-A
Document #: 38-07193 Rev. **
Page 4 of 5
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2411
Document Title: CY2411 54-MHz MPEG Clock Generator with VCXO
Document Number: 38-07193
REV.
**
ECN NO.
110594
Issue
Date
11/07/01
Orig. of
Change
DSG
Description of Change
Change from Spec number: 38-00957 to 38-07193
Document #: 38-07193 Rev. **
Page 5 of 5
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