BU1924 / BU1924F / BU1924FS
Audio ICs
RDS / RBDS decoder
BU1924 / BU1924F / BU1924FS
The BU1924, BU1924F and BU1924FS are RDS / RBDS decoders that employ a digital PLL and have a built-in
anti-aliasing filter and an eight-stage BPF (switched-capacitor filter). Linear CMOS circuitry is used for low power
consumption.
Applications
RDS / RBDS compatible FM receivers for American and European markets, car stereos, high-fidelity stereo systems and
components, and FM pagers.
Features
1) Low current.
2) Two-stage anti-aliasing filter (LPF).
3) 57kHz band-pass filter.
4) DSB demodulation (digital PLL).
5) Quality indication output for demodulated data.
Absolute maximum ratings
(Ta = 25°C)
Parameter
Power supply voltage
Maximum input voltage
Maximum output voltage
Symbol
V
DD
V
Max.
I
Max.
Limits
−0.3~+7.0
−0.3~V
DD
+0.3
±4.0
300
∗
2
(BU1924F)
500
∗
3
(BU1924FS)
Operating temperature
Storage temperature
Topr
Tstg
−40~+85
−55~+125
°C
°C
−
−
1000
∗
1
(BU1924)
Unit
V
V
mA
Conditions
V
DD1
V
DD2
All input pins
All output pins
−
Power dissipation
Pd
mW
∗1
Reduced by 10.0mW for each increase in Ta of 1°C over 25°C.(BU1924)
∗2
Reduced by 3.0mW for each increase in Ta of 1°C over 25°C.(BU1924F)
∗3
Reduced by 5.0mW for each increase in Ta of 1°C over 25°C.(BU1924FS)
Recommended operating conditions
(Ta = 25°C)
Parameter
Power supply voltage
Symbol
V
DD1
V
DD2
Min.
2.7
2.7
Typ.
−
−
Max.
5.5
5.5
Unit
V
V
1/5
BU1924 / BU1924F / BU1924FS
Audio ICs
Block diagram
560p
CMP
(7)
(8)
V
SS3
MUX
270p
(4)
100kΩ
120kΩ
100kΩ
8th Switched
capacitor filter
comparator
Vref
(3)
anti-aliasing
filter
(16) RCLK
2.2µF
V
DD1
(5)
Analog
Power supply
∗1
(1)
QUAL
V
SS1
(6)
∗1
V
DD2
(12)
Digital
Power supply
(11)
PLL
57kH
Z
RDS
PLL
1187.5Hz
Bi-phase
decoder
Differential
decoder
(2)
RDATA
∗2
V
SS2
Reference
clock
(13)
XI
4.332MH
Z
(14)
XO
(10)
Measurement
circuit
(9)
T2
T1
33pF
33pF
∗3
∗3
∗1
: V
DD1
and V
DD2
are separated within the IC.
∗2
: Have V
DD2
(digital power supply) of a sufficiently low impedance.
∗3
: Match the capacitor constants with the crystal manufacturer.
RCLK
(N.C.)
V
DD2
XO
V
SS2
T1
XI
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
V
DD1
V
SS1
RDATA
Vref
QUAL
MUX
V
SS3
CMP
T2
9
2/5
BU1924 / BU1924F / BU1924FS
Audio ICs
Pin descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
QUAL
RDATA
Vref
MUX
V
DD1
V
SS1
V
SS3
CMP
T2
T1
V
SS2
V
DD2
XI
XO
(N.C.)
RCLK
Crystal oscillator
−
Demodulator clock
Digital power supply
2.7V to 5.5V
Connects to 4.332MHz oscillator
(refer to input/output circuits)
−
1187.5Hz clock (refer to the timing diagram)
Test input
Open or connected to ground
Type B
−
Comparator input
C-junction (refer to input/output circuits )
Type D
Analog power supply 2.7V to 5.5V
−
Pin name
Functions
Input/Output type
Type C
Type C
Type E
Type F
Demodulator quality Good data : High, bad data : Low
Demodulator data
Reference voltage
Input
Refer to output data timing
1/2 V
DD1
(refer to input/output circuits)
Composite signal input (refer to input/output circuits)
Type A
−
Type C
Input / Output circuits
Type A
10MΩ
Type B
Type C
Type D
Type E
Type F
VREF
3/5
BU1924 / BU1924F / BU1924FS
Audio ICs
Electrical characteristics
(unless otherwise noted, Ta = 25°C, V
DD1
= V
DD2
= 5.0V, V
SS1
=V
SS2
= V
SS3
= 0.0V)
Parameter
Operating current
Reference voltage
Input current 1
Output current 1
Input current 2
Output current 2
Output high level voltage 1
Output low level voltage 1
〈Filter
block〉
Center frequency
Gain
Attenuation 1
Attenuation 2
Attenuation 3
S / N ratio
〈Demodulator〉
RDS detector sensitivity
RDS input level
Data rate
Clock transient vs. data
Not designed for radiation resistance.
Symbol
I
DD
Vref
I
IN1
I
OUT1
I
IN2
I
OUT2
V
OH1
V
OL1
Min.
−
−
−
−
−
−
V
DD2
−1.0
−
Typ.
6.5
1/2V
DD1
−
−
0.5
0.5
V
DD2
−0.3
0.2
Max.
10.0
−
1.0
1.0
−
−
−
1.0
Unit
mA
V
µA
µA
µA
µA
V
V
I
DD1
+I
DD2
Pin 3
MUX
MUX
XI
XI
Conditions
V
IN
=V
DD1
V
IN
=V
SS1
XI=V
DD2
XI=V
SS2
I
O
=−1.0mA
I
O
=1.0mA
RCLK RDATA QUAL
RCLK RDATA QUAL
FC
GA
ATT1
ATT2
ATT3
SN
56.5
20
18
65
35
−
−
1.0
−
−
57.0
23
22
80
50
35
57.5
26
−
−
−
−
kHz
dB
dB
dB
dB
dB
F=57.0kHz
57kHz±4kHz
38kHz
67kHz
57kHz V
IN
=3.0mVrms
SRDS
VRDS
DRATE
CT
0.5
−
1187.5
4.3
1.0
300
−
−
mVrms
mVrms
Hz
µs
Output data timing
RCLK
RDATA
T
1
T
1
=T
2
=4.3µS
T
5
T
1
T
3
T
3
=T
4
=421µS
T
4
T
5
=T
6
=416.7µS
T
2
T
6
T
2
The clock (RCLK) frequency is 1187.5Hz. Depending on the state of the internal PLL clock, the data (RDATA) is replaced
in synchronous with either the rising or falling or falling edge of the clock. To read the data, you may choose either the
rising or falling edge of the clock as the reference. The data is valid for 416.7µs. after the reference clock edge.
QUAL pin operation : Indicates the quality of the demodulated data.
(1) Good data : HI
(2) Poor data : LO
4/5
BU1924 / BU1924F / BU1924FS
Audio ICs
Electrical characteristic curves
30
20
10
FILTER GAIN : G (
dB)
0
−10
−20
−30
−40
−50
−60
−70
10
20
30 40
50
60
70
80
90 100
FREQUENCY : f (
kHz)
Fig.1 Band-pass filter characteristics
External dimensions
(Units : mm)
BU1924
BU1924F
19.4
±
0.3
16
9
6.5
±
0.3
10.0±0.2
16
6.2±0.3
4.4±0.2
9
1
0.51Min.
3.2
±
0.2 4.25
±
0.3
8
7.62
0.3
±
0.1
0.11
2.54
0.5
±
0.1
0
∼15
1.5±0.1
1
8
1.27
0.4±0.1
0.3Min.
0.15
DIP16
BU1924FS
SOP16
6.6±0.2
16
6.2±0.3
4.4±0.2
9
0.3Min.
1
1.5±0.1
8
0.15±0.1
0.11
0.1
0.8
0.36±0.1
SSOP-A16
0.15±0.1
5/5
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