电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

BUS-61563-28Q

产品描述Micro Peripheral IC
产品类别嵌入式处理器和控制器    微控制器和处理器   
文件大小50KB,共4页
制造商Data Device Corporation
下载文档 详细参数 全文预览

BUS-61563-28Q概述

Micro Peripheral IC

BUS-61563-28Q规格参数

参数名称属性值
包装说明,
Reach Compliance Codeunknown
Base Number Matches1

文档预览

下载PDF文档
BUS-61553
MIL-STD-1553 ADVANCED INTEGRATED
MUX (AIM ) HYBRID
ALSO
SEE
IDE
R’S GU
USE
DESCRIPTION
DDC’s
BUS-61553
Advanced
Integrated Mux (AIM) Hybrid is a
complete
MIL-STD-1553
Bus
Controller (BC), Remote Terminal
Unit (RTU), and Bus Monitor (MT)
device. Packaged in a single 78-pin
DIP package, the BUS-61553 con-
tains dual low-power transceivers,
complete BC/RT/MT protocol logic, a
MIL-STD-1553-to-host interface unit
and 8K x 16 RAM.
Using an industry standard dual
transceiver and standard status and
control signals, the BUS-61553 sim-
plifies system integration at both the
MIL-STD-1553 and host processor
interface levels.
All 1553 operations are controlled
through the CPU access to the
shared 8K x 16 RAM. To ensure
maximum design flexibility, memory
control lines are provided for attach-
ing external RAM to the BUS-61553
address and data buses and for dis-
abling internal memory; the total
combined memory space can be
expanded to 64K x 16. All 1553 trans-
fers are entirely memory-mapped;
thus the CPU interface requires
minimal hardware and/or software
support.
The BUS-61553 operates over the
full military -55°C to +125°C temper-
ature range. Available screened to
MIL-PRF-38534, the BUS-61553 is
ideal for demanding military and
industrial microprocessor-to-1553
interface applications.
FEATURES
• Fully Intergrated Terminal
Including:
–Dual Transceiver
–BC/RT/MT Protocol
–Memory Management Unit
–Processor lnterface Logic
–8K x 16 RAM
• CMOS and Bipolar Technologies
• Internal Interrupt Status and Time
Tag Registers
• High Reliability
• 883B Processing Available
BUS-25679
8
1
DATA
BUS A
2
4
3
TRANSCEIVER A
TX INH
TX
RX
RX
CONTENTION
RESOLVER
INTERRUPT
GENERATOR
CLOCK IN
CHANNEL A
ENCODER/
DECODER
MEMORY
TIMING
CPU
TIMING
MSTRCLR
SELECT
STRBD
READYD
RD/WR
MEM/REG
EXTEN
EXTLD
INT
TRANSFORMER A
768
µs
TIME OUT
PROTOCOL
CONTROLLER
A15-A00
BUS-25679
8
DATA
BUS B
4
1
2
3
TX INH
TX
RX
RX
TRANSCEIVER B
D15-D00
TRANSFORMER B
CHANNEL B
ENCODER/
DECODER
8K x 16
SHARED RAM
PARITY
CHECKER
RT ADDR
RTAD0
RTAD1
RTAD2
RTAD3
RTAD4
RTAD P
RTPARERR
RAM
FIGURE 1. BU-61553 BLOCK DIAGRAM
© 1987, 1999 Data Device Corporation

技术资料推荐更多

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 1787  703  757  415  2027  36  15  16  9  41 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved