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PRELIMINARY
MoBL
®
UniClock CY22M1
Single Output, Low Power Programmable Clock
Generator for Portable Applications
Features
■
■
■
Benefits
■
Small Footprint, 8-Pin QFN 1.7 x 1.7 x 0.6 mm
3
Package
Low Power and Low Jitter Operation
Multiple Operating Voltages:
❐
CY22M1S: 2.5V, 3.0V, or 3.3V
❐
CY22M1L: 1.8V
Programmable Single Output Clock Generator Frequency
Range:
❐
1 to 80 MHz
Crystal or External Reference Clock Input Frequency Range:
❐
Fundamental Tuned Crystal: 8 to 48 MHz
❐
External Reference Clock: 1 to 80 MHz
Programmable Capacitor Tuning Array
Programmable PD# or OE Control Pin
Programmable Asynchronous or Synchronous OE and PD#
Modes
Programmable Output Buffer Drive Strength
Services handsets, portable media players, personal
navigation devices, digital cameras, digital camcorders, and
other portable applications.
Saves PCB space due to small form factor.
Enables quick turnaround as well as flexibility and adaptability
to design changes through programmability.
Enables synthesis of highly accurate and stable output clock
frequencies with zero or low PPM error.
Enables fine tuning of output clock frequency by adjusting the
crystal load C
Load
using programmable internal capacitors.
Lowers clock solution cost by pairing a high frequency PLL
programmability with a low cost, low frequency crystal.
Enables low power during the power down or output disable
function.
Provides flexibility for system applications through selectable
asynchronous or synchronous output enable and disable.
■
■
■
■
■
■
■
■
■
■
■
■
■
Logic Block Diagram
Cypress Semiconductor Corporation
Document Number: 001-49075 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 20, 2009
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PRELIMINARY
MoBL
®
UniClock CY22M1
Pin Description
Figure 1. Package Pinout Drawing: CY22M1 8-Pin 1.7 x 1.7 mm
2
QFN
VDD
8
NC
7
XOUT
1
CY22M1
8-Pin QFN
6
CLKOUT
XIN/CLKIN
2
5
NC
3
PD#/OE
4
GND
Table 1. Pin Definition: CY22M1 8-Pin 1.7 x 1.7 mm
2
QFN
Pin Number
1
2
3
4
5
6
7
8
Name
XOUT
XIN/CLKIN
PD#/OE
GND
NC
CLKOUT
NC
VDD
Input
Input
Power
–
Output
–
Power
IO
Output
Crystal or external clock input.
Multifunction pin. Active low power down or active high output enable pin. Has weak
internal pull up.
Power supply ground.
No connect. Pin has no internal connection.
Programmable clock output. Output voltage depends on VDD. Has weak internal
pull down.
No connect. Pin has no internal connection.
Programmable power supply:
CY22M1S: 2.5V, 3.0V, 3.3V (standard voltage)
CY22M1L: 1.8V (low voltage)
Description
Crystal output. Float for external clock input.
Document Number: 001-49075 Rev. *C
Page 2 of 12
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PRELIMINARY
MoBL
®
UniClock CY22M1
Functional Description
The MoBL
®
UniClock CY22M1 is a programmable, high
accuracy, PLL-based clock generator device designed for low
power, space constrained applications. The low jitter and
accurate outputs makes this device suitable for handsets,
portable media players, personal navigation devices, digital
cameras, digital camcorders, and other portable applications.
The device has several programmable options listed in the
section
Programmable Features
on page 4 of this data sheet.
The entire configuration is one time programmable.
Power Management Feature
The MoBL
®
UniClock CY22M1 offers PD# (active LOW) and OE
(active HIGH) functions. When the power down mode is selected
(PD# =0), the oscillator and PLL are placed in a low supply
current standby mode and the output is tristated and weakly
pulled LOW. The oscillator and PLL circuits must relock when the
part exits the power down mode. If the output is disabled (OE=0),
the output is tristated and weakly pulled LOW. In this mode, the
oscillator and PLL circuits continue to operate, which enables a
rapid return to normal operation when the output is enabled.
In
addition, the PD# or OE mode can be programmed to occur
asynchronously or synchronously with respect to the output
signal. When the asynchronous setting is used, entering power
down or disabling the output occurs immediately (enabling logic
delays) regardless of the position in the clock cycle. Similarly,
exiting power down or enabling the output occurs immediately
with no guarantee of full output clock pulses. However, when the
synchronous setting is used, the part waits for a falling edge at
the output before entering power down or disabling the output.
This prevents output glitches. The first output pulse is
guaranteed to be a full clock pulse when enabling outputs with a
synchronous OE pin. The first output pulse is not guaranteed to
be a full clock when exiting power down in synchronous or
asynchronous mode.
Configurable PLL
The device uses a programmable PLL to generate output
frequencies from 1 to 80 MHz. The high resolution of the PLL and
flexible output dividers provide this flexibility.
Input Reference Clock Option
There is an option of a crystal or clock signal for the input
reference clock. The frequency range for crystal (XIN) is 8 MHz
to 48 MHz, while the range for an external reference clock
(CLKIN) is 1 MHz to 80 MHz. A PLL bypass mode enables this
device to be used as a crystal oscillator.
Multiple VDD Power Supply Option
The device has programmable power supply options. The
operating supply voltages are 2.5V, 3.0V, or 3.3V for CY22M1S
and 1.8V for CY22M1L.
Output Frequency Tuning
The MoBL
®
UniClock CY22M1 contains an on-chip oscillator
with a built-in programmable capacitor array for fine tuning of the
output frequency. The capacitive load seen by the crystal is
adjusted by programming the memory bits. This feature can
compensate for crystal variations or provide a more accurate
synthesized frequency.
Figure 2
on page 4 shows the crystal
oscillator tuning circuit block diagram.
Programmable Output Drive Strength
The DC drive strength of the clock output can be programmed to
one of two settings, enabling control of output rise and fall times.
Table 2
shows the typical rise and fall times for both of the drive
strength settings.
Table 2. Output Drive Strength
Output Drive Strength
Low
High
Rise/Fall Time (ns)
(Typical Value)
2.0
1.0
Document Number: 001-49075 Rev. *C
Page 3 of 12
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PRELIMINARY
MoBL
®
UniClock CY22M1
Crystal Oscillator Tuning Circuit
Table 3. Crystal Oscillator Tuning Capacitor Values
Cap
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
Value
[1]
5.000
2.500
1.250
0.625
0.313
0.156
0.078
0.039
Unit
pF
pF
pF
pF
pF
pF
pF
pF
Figure 2. Crystal Oscillator Tuning Block Diagram
F
XIN,
ESR, C
0
R
F
-R
C
PXIN
C
XIN
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
C
XOUT
C
PXOUT
X0
X1
X2
X3
X4
X5
X6
X7
X7
X6
X5
X4
X3
X2
X1
X0
Programmable Features
The following list of features can be custom configured:
■
■
■
■
■
■
■
Programming Support
The device is available in factory and field programmable
versions. The CyClockMaker Programming kit along with
CyClockDesigner configuration software is used for field
programming the device. For specific programming needs,
contact your local Cypress field application engineer (FAE) or
sales representative.
PLL frequency and output divider value
Oscillator tuning (crystal load) capacitance value
Direct oscillator output (PLL bypass)
High or low power supply voltage operation
Power management mode (OE or PD#)
Power management timing (synchronous or asynchronous)
Programmable output drive strength
Note
1. The capacitor values are nominal.
Document Number: 001-49075 Rev. *C
Page 4 of 12
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