DATASHEET
USER CONFIGURABLE DIVIDER
Description
The ICS674-01 consists of two separate configurable
dividers. The A Divider is a 7-bit divider and can divide by 3
to 129. The B Divider consists of a 9-bit divider followed by
a post divider. The 9-bit divider can divide by 12 to 519. The
post divider has eight settings of 1, 2, 4, 5, 6, 7, 8, and 10;
giving a maximum total divide of 5190. The A and B
Dividers can be cascaded to give a maximum divide of
669510. The ICS674-01 supports the ICS673 PLL Building
Block and enables the user to build a full custom PLL
synthesizer.
ICS674-01
Features
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Packaged in 28-pin SSOP (150 mil body)
Available in Pb (lead) free package
General purpose programmable divider
Supports ICS673 PLL Building Block
User determines the divide by setting input pins
Pull-ups on all select inputs
Includes one 7-bit Divider for OUTA
Includes one 9-bit Divider and one selectable Post
Divider for OUTB
Industrial temperature range available
25 mA drive capability at TTL levels
Advanced, low power CMOS process
Operating voltage of 3.3 V or 5 V
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Block Diagram
A6:A0
7
VDD
2
INA
Divider A
(7-Bit)
OUTA
INB
Divider B
(9-Bit)
3
Post
Divider
OUTB
9
B8:B0
GND
3
S2:S0
IDT™ / ICS™
USER CONFIGURABLE DIVIDER
1
ICS674-01
REV G 110409
ICS674-01
USER CONFIGURABLE DIVIDER
CLOCK DIVIDER
Pin Assignment
A5
A6
S0
S1
S2
VDD
INA
INB
GND
B0
B1
B2
B3
B4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A4
A3
A2
A1
A0
VDD
OUTA
OUTB
GND
GND
B8
B7
B6
B5
Post Divider Table
S2
Pin 5
0
0
0
0
1
1
1
1
S1
Pin 4
0
0
1
1
0
0
1
1
S0
Pin 3
0
1
0
1
0
1
0
1
Post Divide
10
2
8
4
5
7
1
6
28 pin (150 mil) SSOP
Pin Descriptions
Pin
Number
1, 2, 24 - 28
3-5
6, 23
7
8
9, 19 - 20
10 - 18
21
22
Pin
Name
A5, A6, A0-A4
S0, S1, S2
VDD
INA
INB
GND
B0 - B8
OUTB
OUTA
Pin Type
Input
Input
Power
Input
Input
Power
Input
Output
Output
Pin Description
Divider A word input pins. Forms a number from 1 to 127. Internal pull-up
resistors. See page 3 for details.
Select pins for Post Divider. See table above. Internal pull-up resistors.
Connect to VDD.
Divider A input.
Divider B input.
Connect to ground.
Divider B word input pins. Forms a number from 4 to 511. Internal pull-up
resistors. See page 3 for details.
Divider B output.
Divider A output.
IDT™ / ICS™
USER CONFIGURABLE DIVIDER
2
ICS674-01
REV G 110409
ICS674-01
USER CONFIGURABLE DIVIDER
CLOCK DIVIDER
External Components
The ICS674-01 requires a minimum number of external components for proper operation. A 0.01µF decoupling
capacitor should be connected between each VDD and GND as close to the device as possible. A series
termination resistor of 33Ω should be used in series with OUTA and OUTB pins.
Determining (setting) the Divider
The user has full control in setting the desired divide. The user should connect the appropriate divider select input
pins directly to ground (or VDD, although this is not required because of internal pull-ups) during Printed Circuit
Board layout, ensuring that the ICS674-01 will automatically produce the correct divide when all components are
soldered. It is also possible to connect the inputs to parallel I/O ports in order to change divides. The divides of the
ICS674-01 can be determined by the following equations:
Divide A = DAW + 2
Where
Divider A Word (DAW) = 1 to 127 (0 is not permitted)
Divide B = (DBW+8) x PD
Where
Divider B Word (DBW) = 4 to 511 (0, 1, 2, 3 are not permitted)
Post Divider (PD) = values on page 2
For example, suppose Divide A is desired to be 61 and Divide B is desired to be 284, then DAW = 59,
DBW = 276, and PD = 1. This means A6:A0 is 0111011, B8:B0 is 100010100 and S2:S0 is 110. Since all inputs
have pull-ups, it is only necessary to ground the zero pins, namely A6, A2, B7, B6, B5, B1, B0, and S0.
These configuration pins can be changed at any time during operation.
IDT™ / ICS™
USER CONFIGURABLE DIVIDER
3
ICS674-01
REV G 110409
ICS674-01
USER CONFIGURABLE DIVIDER
CLOCK DIVIDER
Using the ICS674-01 with the ICS673-01:
The ICS674-01 may be used with the ICS673-01 to build a frequency synthesizer. The following example shows a typical
application when the reference clock is in the MHz range:
Reference Clock
Divide A
REFIN
ICS673-01
FBIN
Post
Divide
CLK1
Ouput Clock
CLK2
Divide B
ICS674-01
If the reference is in the kHz range, for example 8 kHz, the following configuration may be more typical:
Reference Clock
REFIN
ICS673-01
FBIN
Divide A
ICS674-01
Post
Divide
CLK1
Ouput Clock
CLK2
Divide B
Note that in both examples, Divide B is connected to the output of the ICS673. This is because Divide B has a higher
operating frequency than Divide A.
IDT™ / ICS™
USER CONFIGURABLE DIVIDER
4
ICS674-01
REV G 110409
ICS674-01
USER CONFIGURABLE DIVIDER
CLOCK DIVIDER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS674-01. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
CLKIN and FBIN inputs
Electrostatic Discharge
Ambient Operating Temperature
Ambient Operating Temperature (I version)
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
-0.5 V to 5.5 V
2000 V
0 to +70° C
-40 to +85° C
-65 to +150° C
150° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.0
Typ.
Max.
+70
+5.5
Units
°
C
V
DC Electrical Characteristics
VDD=5 V ±10%,
Ambient temperature -40 to +85° C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Operating Supply Current
DivA=DivB=20
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
IDD
Conditions
All A, B, and S pins
All A, B, and S pins
INA and INB only
INA and INB only
I
OH
= -25 mA
I
OL
= 25 mA
No load, f
in
=100 MHz
3.3 V
No load, f
in
=100 MHz
5V
Min.
3.0
2
Typ.
Max.
5.5
0.8
Units
V
V
V
V
V
V
V
mA
mA
(VDD/2)+1 VDD/2
VDD/2
2.4
0.4
3
5
(VDD/2)-1
IDT™ / ICS™
USER CONFIGURABLE DIVIDER
5
ICS674-01
REV G 110409
微控制器 MCU
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