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CY62127DV30
MoBL
®
1-Mb (64K x 16) Static RAM
Features
• Temperature Ranges
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
• Very high speed: 45 ns
• Wide voltage range: 2.2V to 3.6V
• Pin compatible with CY62127BV
• Ultra-low active power
— Typical active current: 0.85 mA @ f = 1 MHz
— Typical active current: 5 mA @ f = f
MAX
• Ultra-low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• Packages offered in a 48-ball FBGA and a 44-lead TSOP
Type II
• Also available in Lead-Free 48-ball FBGA, 56-pin QFN
and 44-lead TSOP Type II packages
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected (CE
HIGH or both BHE and BLE are HIGH). The input/output pins
(I/O
0
through I/O
15
) are placed in a high-impedance state
when: deselected (CE HIGH), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH) or during a write operation (CE
LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes
.
Functional Description
[1]
The CY62127DV30 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
10
ROW DECODER
64K x 16
RAM Array
2048 x 512
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
CE
BHE
BLE
A
11
Pow -Down
er
Circuit
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
A
12
A
13
A
14
A
15
Cypress Semiconductor Corporation
Document #: 38-05229 Rev. *F
• 3901 North First Street
• San Jose
,
CA 95134
• 408-943-2600
Revised June 6, 2005
CY62127DV30
MoBL
®
Product Portfolio
Power Dissipation
Operating, I
CC
(mA)
V
CC
Range (V)
Product
CY62127DV30L
CY62127DV30LL
CY62127DV30L
CY62127DV30LL
CY62127DV30L
CY62127DV30LL
2.2
2.2
2.2
3.0
3.0
3.0
3.6
3.6
3.6
Min.
2.2
Typ.
3.0
Max.
3.6
Speed
(ns)
45
45
55
55
70
70
f = 1 MHz
Typ
[4]
f = f
MAX
Typ.
[4]
Standby I
SB2
(µA)
Range
Ind’l
Ind’l
Ind’l
Auto
Ind’l
Ind’l
Ind’l
Typ.
[4]
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Max.
5
4
5
15
4
5
4
Max.
1.5
1.5
1.5
1.5
1.5
1.5
Max.
13
13
10
10
10
10
0.85
0.85
0.85
0.85
0.85
0.85
6.5
6.5
5
5
5
5
Pin Configurations
[2, 3]
1
BLE
I/O
8
I/O
9
V
SS
V
CC
I/O
14
I/O
15
NC
FBGA (Top View)
4
2
5
3
OE
BHE
I/O
10
I/O
11
A
0
A
3
A
5
NC
A
1
A
4
A
6
A
7
NC
A
15
A
13
A
10
A
2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
NC
I/O
0
I/O
2
V
CC
V
SS
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
TSOP II (Forward)
Top View
A
4
A
3
A
2
A
1
A
0
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
15
A
14
A
13
A
12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
I/O
12
DNU
I/O
13
NC
A
8
A
14
A
12
A
9
A
5
A
6
A
7
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
8
A
9
A
10
A
11
NC
Notes:
2. NC pins are not connected to the die.
3. E3 (DNU) can be left as NC or Vss to ensure proper operation. (Expansion Pins on FBGA Package: E4 - 2M, D3 - 4M, H1 - 8M, G2 - 16M, H6 - 32M).
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25°C.
Document #: 38-05229 Rev. *F
Page 2 of 12
CY62127DV30
MoBL
®
Pin Configurations
(continued)
BHE
A
12
A
10
A
15
A
14
A
13
A
11
NC
56
NC
55
NC
NC
OE
A
9
A
8
54
53
52
51
50
49
48
47
46
45
44
43
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
0
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
42
41
40
39
38
37
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
A
7
A
6
NC
56-pin QFN
36
35
34
33
32
31
30
29
A
2
Document #: 38-05229 Rev. *F
NC
NC
A
3
NC
NC
DNU
A
4
NC
NC
A
5
NC
NC
NC
Page 3 of 12
CY62127DV30
MoBL
®
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential
.........................................................................
−0.3V
to 3.9V
DC Voltage Applied to Outputs
in High-Z State
[5]
....................................−0.3V to V
CC
+ 0.3V
DC Input Voltage
[5]
................................
−0.3V
to V
CC
+ 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Range
Industrial
Automotive
Ambient Temperature (T
A
)
–40°C to +85°C
–40°C to +125°C
V
CC
[6]
2.2V to 3.6V
2.2V to 3.6V
DC Electrical Characteristics
(Over the Operating Range)
-45
Parameter
V
OH
V
OL
V
IH
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Test Conditions
2.2 < V
CC
< 2.7 I
OH
=
−0.1
mA
2.7 < V
CC
< 3.6 I
OH
=
−1.0
mA
2.2 < V
CC
< 2.7 I
OL
= 0.1 mA
2.7 < V
CC
< 3.6 I
OL
= 2.1 mA
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
V
IL
I
IX
I
OZ
Input LOW
Voltage
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
Ind’l
Auto
−1
+1
1.8
2.2
−0.3
−0.3
−1
2.0
2.4
0.4
0.4
V
CC
1.8
+ 0.3
V
CC
2.2
+ 0.3
0.6
0.8
+1
−0.3
−0.3
−1
−4
−1
−4
6.5
0.85
1.5
1.5
13
1.5
5
4
5
0.85
1.5
1.5
1.5
2.0
2.4
0.4
0.4
V
CC
1.8
+ 0.3
V
CC
2.2
+ 0.3
0.6
−0.3
0.8
−0.3
+1
+4
+1
+4
10
1.5
5
15
4
1.5
4
5
0.85
1.5
10
1.5
5
µA
−1
+1
−1
-55
2.0
2.4
0.4
0.4
V
CC
+ 0.3
V
CC
+ 0.3
0.6
0.8
+1
µA
µA
µA
µA
mA
V
V
V
-70
V
Min. Typ.
[4]
Max. Min. Typ.
[4]
Max. Min Typ.
[4]
Max. Unit
Input Leakage GND < V
I
< V
CC
Current
Output
Leakage
Current
GND < V
O
< V
CC
, Output Ind’l
Disabled
Auto
I
CC
V
CC
Operating f = f
MAX
= 1/t
RC
V
CC
= 3.6V,
Supply Current
I
OUT
= 0 mA,
f = 1 MHz
CMOS level
Automatic CE
Power-down
Current—
CMOS Inputs
CE > V
CC
−
0.2V,
L Ind’l
V
IN
> V
CC
−
0.2V, V
IN
Auto
< 0.2V,
f = f
MAX
(Address and LL
Data Only),
f = 0 (OE, WE, BHE
and BLE)
CE > V
CC
−
0.2V,
V
IN
> V
CC
−
0.2V or
V
IN
< 0.2V,
f = 0, V
CC
= 3.6V
L Ind’l
Auto
LL
I
SB1
I
SB2
Automatic CE
Power-down
Current—
CMOS Inputs
1.5
1.5
5
4
1.5
1.5
1.5
5
15
4
1.5
1.5
5
4
µA
Notes:
5. V
IL(min.)
=
−2.0V
for pulse durations less than 20 ns., V
IH(max.)
= Vcc+0.75V for pulse durations less than 20 ns.
6. Full device operation requires linear ramp of V
CC
from 0V to V
CC(min)
& V
CC
must be stable at V
CC(min)
for 500
µs.
Document #: 38-05229 Rev. *F
Page 4 of 12
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