MM74HC573 3-STATE Octal D-Type Latch
September 1983
Revised May 2000
MM74HC573
3-STATE Octal D-Type Latch
General Description
The MM74HC573 high speed octal D-type latches utilize
advanced silicon-gate P-well CMOS technology. They pos-
sess the high noise immunity and low power consumption
of standard CMOS integrated circuits, as well as the ability
to drive 15 LS-TTL loads. Due to the large output drive
capability and the 3-STATE feature, these devices are ide-
ally suited for interfacing with bus lines in a bus organized
system.
When the LATCH ENABLE(LE) input is HIGH, the Q out-
puts will follow the D inputs. When the LATCH ENABLE
goes LOW, data at the D inputs will be retained at the out-
puts until LATCH ENABLE returns HIGH again. When a
HIGH logic level is applied to the OUTPUT CONTROL OC
input, all outputs go to a HIGH impedance state, regardless
of what signals are present at the other inputs and the state
of the storage elements.
The 74HC logic family is speed, function and pinout com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to V
CC
and ground.
Features
s
Typical propagation delay: 18 ns
s
Wide operating voltage range: 2 to 6 volts
s
Low input current: 1
µ
A maximum
s
Low quiescent current: 80
µ
A maximum (74HC Series)
s
Compatible with bus-oriented systems
s
Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number
MM74HC573WM
MM74HC573SJ
MM74HC573MTC
MM74HC573N
Package Number
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Output
Control
L
L
L
H
Latch
Enable
H
H
L
X
H
L
X
X
H
L
Q
0
Z
Data
Output
H
=
HIGH Level
L
=
LOW Level
Q
0
=
Level of output before steady-state input conditions were established.
Z
=
High Impedance
X
=
Don't Care
Top View
© 2000 Fairchild Semiconductor Corporation
DS005212
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MM74HC573
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
, I
OK
)
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current, per pin (I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
S.O. Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
°
C
600 mW
500 mW
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times
(t
r
, t
f
)
V
CC
=
2.0V
V
CC
=
4.5V
V
CC
=
6.0V
1000
500
400
ns
ns
ns
2
0
Max
6
V
CC
Units
V
V
−
0.5 to
+
7.0V
−
1.5 to V
CC
+
1.5V
−
0.5 to V
CC
+
0.5V
±
20 mA
±
35 mA
±
70 mA
−
65
°
C to
+
150
°
C
−
40
+
85
°
C
Note 1:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating — plastic “N” package:
−
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
Symbol
V
IH
Parameter
Minimum HIGH Level Input
Voltage
V
IL
Maximum LOW Level Input
Voltage
V
OH
Minimum HIGH Level Output
Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
Conditions
(Note 4)
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0
4.5
6.0
4.2
5.7
0
0
0
0.2
0.2
T
A
=
25°C
Typ
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
±0.5
8.0
1.0
0.6
0.4
1.5
0.8
0.5
T
A
= −40
to 85°C T
A
= −55
to 125°C
Guaranteed Limits
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
±5.0
80
1.8
1.0
0.6
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
±10
160
2.0
1.1
0.7
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
mA
mA
mA
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
6.0 mA
|I
OUT
|
≤
7.8 mA
V
OL
Maximum LOW Level Output
Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
2.0V
4.5V
6.0V
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
6.0 mA
|I
OUT
|
≤
7.8 mA
I
IN
I
OZ
I
CC
∆I
CC
Maximum Input Current
Maximum 3-STATE Output
Leakage Current
Maximum Quiescent Supply
Current
Quiescent Supply Current
per Input Pin
V
IN
=
V
CC
or GND
V
OUT
=
V
CC
or GND
OC
=
V
IH
V
IN
=
V
CC
or GND
I
OUT
=
0
µA
V
CC
=
5.5V
V
IN
=
2.4V
or 0.4V (Note 4)
6.0V
OE
LE
DATA
6.0V
4.5V
6.0V
6.0V
4.5V
6.0V
Note 4:
For a power supply of 5V
±10%
the worst-case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst-case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst-case leakage cur-
rent (I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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2
MM74HC573
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25
°
C, t
r
=
t
f
=
6 ns
Symbol
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PZH
, t
PZL
t
PHZ
, t
PLZ
t
S
t
H
t
W
Parameter
Maximum Propagation Delay, Data to Q
Maximum Propagation Delay, LE to Q
Maximum Output Enable Time
Maximum Output Disable Time
Minimum Set Up Time, Data to LE
Minimum Hold Time, LE to Data
Minimum Pulse Width, LE or Data
C
L
=
45 pF
C
L
=
45 pF
R
L
=
1 kΩ
C
L
=
45 pF
R
L
=
1 kΩ
C
L
=
5 pF
10
2
10
15
5
16
ns
ns
ns
13
23
ns
Conditions
Typ
16
14
15
Guaranteed
Limit
20
22
27
Units
ns
ns
ns
AC Electrical Characteristics
Symbol
t
PHL
, t
PLH
Parameter
Maximum Propagation
Delay Data to Q
Conditions
C
L
=
50 pF
C
L
=
150 pF
C
L
=
50 pF
C
L
=
150 pF
C
L
=
50 pF
C
L
=
150 pF
t
PHL
, t
PLH
Maximum Propagation
Delay, LE to Q
C
L
=
50 pF
C
L
=
150 pF
C
L
=
50 pF
C
L
=
150 pF
C
L
=
50 pF
C
L
=
150 pF
t
PZH
, t
PZL
Maximum Output Enable
Time
R
L
=
1 kΩ
C
L
=
50 pF
C
L
=
150 pF
C
L
=
50 pF
C
L
=
150 pF
C
L
=
50 pF
C
L
=
150 pF
t
PHZ
, t
PLZ
Maximum Output Disable
Time
t
S
Minimum Set Up Time
Data to LE
t
H
Minimum Hold Time
LE to Data
t
W
Minimum Pulse Width LE,
or Data
t
TLH
, t
THL
Maximum Output Rise
and Fall Time, Clock
C
PD
C
IN
Power Dissipation Capacitance
(Note 5) (per latch)
Maximum Input
Capacitance
OC
=
V
CC
OC
=
GND
C
L
=
50 pF
R
L
=
1 kΩ
C
L
=
50 pF
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
30
9
8
25
7
6
5
52
5
10
10
10
55
67
15
24
14
22
40
13
12
30
10
9
140
180
28
36
24
31
125
25
21
75
15
13
25
5
4
80
16
14
60
12
10
175
225
35
45
30
39
156
31
27
95
19
16
31
6
5
100
20
18
75
15
13
210
270
42
54
36
47
188
38
32
110
22
19
38
7
6
120
24
20
90
18
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
pF
V
CC
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
T
A
=
25°C
Typ
45
58
17
21
15
19
46
60
14
21
12
19
110
150
22
30
19
26
115
155
23
31
20
27
T
A
= −40
to 85°C T
A
= −55
to 125°C
Guaranteed Limits
138
188
28
38
24
33
138
194
29
47
25
34
165
225
33
40
29
39
165
233
35
47
30
41
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
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