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CAT24WC66
64K-Bit I
2
C Serial CMOS EEPROM
FEATURES
s
400 kHz I
2
C bus compatible*
s
1.8 to 6 volt read and write operation
s
Cascadable for up to eight devices
s
32-byte page write buffer
s
Self-timed write cycle with auto-clear
s
Schmitt trigger inputs for noise protection
s
Zero standby current
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
s
Commercial, industrial and automotive
temperature ranges
s
Write protection
–Top 1/4 array protected when WP at V
IH
s
1,000,000 program/erase cycles
s
100 year data retention
s
8-pin DIP or 8-pin SOIC packages
DESCRIPTION
The CAT24WC66 is a 64K-bit Serial CMOS EEPROM
internally organized as 8192 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The
CAT24WC66 features a 32-byte page write buffer. The
device operates via the I
2
C bus serial interface and is
available in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
DIP Package (P, L)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
BLOCK DIAGRAM
EXTERNAL LOAD
DOUT
ACK
VCC
VSS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
256
SENSE AMPS
SHIFT REGISTERS
SOIC Package (J, K, W, X)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
SDA
START/STOP
LOGIC
XDEC
WP
CONTROL
LOGIC
256
EEPROM
256 X 256
PIN FUNCTIONS
Pin Name
A0, A1, A2
SDA
SCL
WP
V
CC
V
SS
Function
Device Address Inputs
Serial Data/Address
Serial Clock
Write Protect
+1.8V to +6V Power Supply
Ground
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
HIGH VOLTAGE/
TIMING CONTROL
DATA IN STORAGE
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1037, Rev. E
1
CAT24WC66
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
........... –2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25°C) ................................... 1.0W
RELIABILITY CHARACTERISTICS
Symbol
NEND
(3)
TDR
(3)
VZAP
(3)
ILTH
(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100mA
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Max
Units
Cycles/Byte
Years
Volts
mA
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Symbol
I
CC
I
SB(5)
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
Parameter
Power Supply Current
Standby Current (VCC = 5V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
(V
CC
= +3.0V)
Output Low Voltage
(V
CC
= +1.8V)
I
OL
= 3.0 mA
I
OL
= 1.5 mA
Test Conditions
f
SCL
= 100 kHz
V
IN
= GND or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
-1
V
CC
x 0.7
Min
Typ
Max
3
0
10
10
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.5
Units
mA
µA
µA
µA
V
V
V
V
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
I/O(3)
C
IN(3)
Parameter
Input/Output Capacitance
(SDA)
Input Capacitance
(A0, A1, A2, SCL, WP)
Conditions
V
I/O
= 0V
V
IN
= 0V
Min
Typ
Max
8
6
Units
pF
pF
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) Standby current (I
SB
) = 0
µA
(<900 nA).
Doc. No. 1037, Rev. E
2
CAT24WC66
A.C. CHARACTERISTICS
V
CC
= +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
1.8V - 2.5V
Symbol
FSCL
T
I(1)
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
Parameter
Min
Clock Frequency
Noise Suppression Time Constant at
SCL, SDA Inputs
SCL Low to SDA Data Out and
ACK Out
Time the Bus Must be Free Before a
New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a
Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
4
100
4.7
4
4.7
4
4.7
0
50
1
300
Max
100
200
3.5
4.5V - 5.5V
Units
Min
Max
400
200
1
1.2
0.6
1.2
0.6
0.6
0
50
0. 3
300
0.6
100
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Power-Up Timing
(1)(2)
Symbol
t
PUR
t
PUW
Parameter
Power-Up to Read Operation
Power-Up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Write Cycle Limits
Symbol
t
WR
Parameter
Write Cycle Time
Min
Typ
Max
10
Units
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
3
Doc. No. 1037, Rev. E
CAT24WC66
FUNCTIONAL DESCRIPTION
The CAT24WC66 supports the I
2
C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. The
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. The CAT24WC66 operates
as a Slave device. Both the Master device and Slave
device can operate as either transmitter or receiver, but
the Master device controls which mode is activated.
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
A0, A1, A2:
Device Address Inputs
These pins are hardwired or left unconnected (for
hardware compatibility with CAT24WC16). When
hardwired, up to eight CAT24WC66 devices may be
addressed on a single bus system (refer to Device
Addressing ). When the pins are left unconnected, the
default values are zeros.
WP:
Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the top
1/4 array of memory is write protected. When left
floating, memory is unprotected.
PIN DESCRIPTIONS
SCL:
Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
SDA:
Serial Data/Address
The bidirectional serial data/address pin is used to
Figure 1. Bus Timing
tF
tLOW
tHIGH
tLOW
tR
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
SDA IN
tAA
Figure 2. Write Cycle Timing
tDH
tBUF
SCL
SDA
8TH BIT
BYTE n
ACK
Figure 3. Start/Stop Timing
SDA
SCL
Doc. No. 1037, Rev. E
4
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