LDS8161/41
6-Channel / 4-Channel High-Side Linear WLED Driver
with LED Temperature Compensation Using LED-Sense
TM
, I
2
C, and Digital PWM
FEATURES
•
•
Six (8161) / or Four (8141) Power-Lite Linear LDO
current regulators with 50 mV dropout in a high-
side driver topology.
High temperature LED current de-rating using the
TM
LED-Sense temperature compensation algorithm,
which directly monitors an LED PN junction. No
external temperature sensor is required.
2
I C compatible serial programming interface
2
LED current programmable via I C from 0 to
~32 mA in 256 linear steps. Three (8161) or two
(8141) separately controlled driver banks with 2
LED drivers each
Integrated PWM generator for LED dimming with
2
12-bit resolution and 256 I C-programmable
logarithmic duty cycle steps from 0% to 100%
(~0.17 dB per step)
Total combined dimming range of > 16,384:1
Power efficiency up to 98%; average efficiency
> 80% in Li-ion battery applications
Low current shutdown mode ( < 1 µA );
Soft start and current limiting
LED Short circuit detection and protection, LED
open detection
Thermal shutdown protection
Low EMI.
Available in 3 mm x 3 mm x 0.8 mm 16-pin TQFN
package
TM
•
•
•
•
•
•
•
•
•
•
•
The LDO drivers have a low dropout voltage of
50 mV typically at maximum rated current. This
provides a low power/low EMI solution in Li-ion
battery applications without voltage boosting and
associated external capacitors and components.
High temperature current de-rating insures LED
reliability and provides automatic adjustment of LED
current to achieve maximum specified LED
brightness across the ambient temperature range.
TM
The
proprietary
LED-Sense
temperature
compensation algorithm directly monitors the junction
temperature of an LED and applies current de-rating
per a user loadable LUT (look up table) in 5ºC steps.
No external temperature-sensing device is needed.
An integrated 12-bit PWM generator with “smooth”
logarithmic control supports LED dimming and high
temperature current de-rating. The PWM duty cycle is
2
programmable via the I C serial interface from 0% to
100%. User programmed 8-bit codes are converted
to 12-bit resolution logarithmic steps of ~ 0.17 dB per
step. The PWM frequency is ~280 Hz to minimize
noise generation.
The EN logic input functions as a chip enable. A logic
HIGH applied at the EN pin allows the
2
LDS8161/LDS8141
to
respond
to
IC
communications. An external serial interface address
pin is available for use in multi-target applications.
The device operates from 2.5V to 5.5V.
The LDS8160 is available in a 3 x 3 x 0.8 mm
16-lead TQFN package.
3
APPLICATIONS
•
•
•
Keypad and Display Backlight
Cellular Phone
PDAs and Smartphones
DESCRIPTION
The LDS8161 is a 6-channel and the LDS8141 is a 4-
channel linear LED driver for WLED applications. It
includes ultra low dropout LDO current regulators at a
maximum 31.875 mA per channel in a common
cathode high side driver topology.
The LDS8161/LDS8141 has an average efficiency of
> 80% in Li-ion battery applications. It includes three
(LDS8161) or two (LDS8141) 8-bit current setting
DACs (one per bank) allowing LED currents to be
2
programmed via an I C-compatible serial interface
from 0 to 31.875 mA in 256 steps of 125µA per step.
© 2013 IXYS Corp.
Characteristics subject to change without notice
1
Doc. No. 8141/61_DS, Rev. N1.1
LDS8161/41
RECOMMENDED OPERATING CONDITIONS
Parameter
V
IN
I
LED
per LED pin
Total Output Current I
LOAD
Junction Temperature Range
Rating
2.5 to 5.5
0 – 31.875
191.25
-40 to +125
Unit
V
mA
mA
°C
Typical application circuit with external components is shown on page 1.
ELECTRICAL OPERATING CHARACTERISTICS
(Over recommended operating conditions unless specified otherwise) V
IN
= 3.6V, C
IN
= 1 µF, EN = High, T
AMB
= 25°C
Name
LEDx Channel Current DAC Range
# of LEDx Current steps (linear steps)
LEDx Current DAC Resolution/step
EN = V
IN
6/4 Channels at 100%
Quiescent Current
DC PWMs and Temp
De-Rating Active
Conditions
Min
0
2
Typ
256
0.125
125
0.6/0.45
0.45/0.35
0.5
±1.5
±1.5
2
1
50
285
256
13.7
12
0.17
Max
31.875
Shutdown Current
LED Current Accuracy
LED Channel Matching
Line Regulation
1
Load Regulation
2
Dropout Voltage
PWM Frequency
# of PWM duty cycle steps
Standby (no I C clock)
I
LOAD
= 120 mA/ 80 mA
I
LOAD
= 60 mA / 40 mA
V
EN
= 0V
5 mA
≤
I
LED
≤
30 mA
(I
LED
- I
LEDAVG
) / I
LEDAVG
2.7 V
≤
V
IN
≤
4.2 V
0.2 V < Vdx < 1.2 V
1 mA
≤
I
LED
≤
30 mA
0.35
1
75
Units
mA
steps
mA
µA
mA
mA
µA
%
%
%/V
%/V
mV
Hz
µs
bits
dB
PWM
0
Steps/5 C
0
C
0
Minimum PWM On Time
PWM resolution
PWM Step Size
#
of
∆PWM
Steps for current de-rating
De-rating Temperature Adjust Steps
Programmable De-rating Start
Temperature (Tj) Range (typical)
Programmable LED Shutdown
Temperature(Tj) Range (typical)
Active or Normal Standby
mode; EN = V
IN
Shutdown
Active or Normal Standby
Mode
Shutdown
1-x Scale Mode
2-x Scale Mode
-7
-14
0
0
5
55
105
80
120
1
0.1
V
IN
0.4
150
20
10
250
0.4
30
80
-1
-0.1
1.2
0
C
C
0
Input current
EN Pin
Logic Level
High
Low
Thermal Shutdown
Thermal Hysteresis
Wake-up/Shutdown Delay Time from EN
Raising/Falling Edge
3
Output short circuit Threshold
Note:
µA
V
°C
ms
ms
V
Soft ramp disabled
Soft ramp enabled
I
LED
= 20 mA
1. Vdx = Vin – V
F
,
2. Vdx = Vin – V
F
, at which I
ILED
decreases by 10% from set value
3. Minimum LED forward voltage, which will be interpreted as “LED SHORT” condition
© 2013 IXYS Corp.
Characteristics subject to change without notice
3
Doc. No. 8141/61_DS, Rev. N1.1
LDS8161/41
I
2
C CHARACTERISTICS
Over recommended operating conditions unless otherwise specified for 2.7
≤
VIN
≤
5.5V, over full ambient temperature range -40 to +85ºC.
Symbol
f
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
t
BUF
t
AA
t
DH
Parameter
SCL Clock Frequency
Hold Time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up Time for a repeated START condition
Data In Hold Time
Data In Set-up Time
Rise Time of both SDAT and SCLK signals
Fall Time of both SDAT and SCLK signals
Set-up Time for STOP condition
Bus Free Time between a STOP and START condition
SCLK Low to SDAT Data Out and ACK Out
Data Out Hold Time
Min
0
0.6
1.3
0.6
0.6
0
100
Max
400
0.9
300
300
0.6
1.3
0.9
300
Unit
kHz
µs
µs
µs
µs
ns
ns
ns
ns
µs
µs
µs
ns
Figure 1: I C Bus Timing Diagram
2
READ OPERATION:
Option 1:
Standard protocol sequential read:
S
Slave Address
R
A
Data 0
A
Data 1
A
Data 2
Reg. m+2
Data n
Reg. m+n,
A*
P
From: Reg. m Reg. m+1
where Reg. m is the last addressed in the write operation register
Option 2:
Random access:
S
Slave Address
R
A
Data m
A*
P
From reg. m, where Reg. m is the last addressed in the write operation register
Option 3:
Random access with combined (extended) protocol:
S
Slave Address
W
A
Register Address m
A
Sr
Slave Address
R
A
Data m
A*
P
WRITE OPERATION:
Option 1:
Standard protocol sequencial write:
S
Slave Address
W
A
Register Address m
A
Data 0
A
Data 1
Reg. m+1
A
Data 2
Reg. m+2
Data k
Reg. m+k
A*
P
To: Reg. m
© 2013 IXYS Corp.
Characteristics subject to change without notice
4
Doc. No. 8141/61_DS, Rev. N1.1
LDS8161/41
Option 2:
Combined (extended) protocol:
S
Slave Address
W
A
Register Address m
A
Sr
Slave Address
W
A
Data
A*
P
To: Reg. m
S: Start Condition
Sr Start Repeat Condition
R, W: Read bit (1), Write bit (0)
A: Acknowledge (SDAT high)
A*: Not Acknowledge (SDAT low)
P: Stop Condition
Slave Address: Device address 7 bits (MSB first).
Register Address: Device register address 8 bits
Data: Data to read or write 8 bits
- send by master
- send by slave
I
2
C BUS PROTOCOL
Standard protocol
Combined protocol:
WRITE INSTRUCTION SEQUENCE
Standard protocol:
Write Instruction Example - Setting 20mA Current in LEDB1 and LEDB2
© 2013 IXYS Corp.
Characteristics subject to change without notice
5
Doc. No. 8141/61_DS, Rev. N1.1
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