TSPC603R
in PQFP package
PowerPC 603e™ RISC MICROPROCESSOR Family
PID7t-603e Specification
DESCRIPTION
The PID7t-603e implementation of PowerPC603e (after
named 603r) is a low-power implementation of reduced
instruction set computer (RISC) microprocessors PowerPC™
family. The 603r implements 32-bit effective addresses, inte-
ger data types of 8, 16 and 32 bits, and floating-point data types
of 32 and 64 bits.
The 603r is a low-power 2.5/3.3-volt design and provides four
software controllable power-saving modes.
The 603r is a superscalar processor capable of issuing and
retiring as many as three instructions per clock. Instructions
can execute out of order for increased performance ; however,
the 603r makes completion appear sequential. The 603r inte-
grates five execution units and is able to execute five instruc-
tions in parallel.
The 603r provides independent on-chip, 16-Kbyte, four-way
set-associative, physically addressed caches for instructions
and data and on-chip instruction and data memory manage-
ment units (MMUs). The MMUs contain 64-entry, two-way set-
associative, data and instruction translation lookaside buffers
that provide support for demand-paged virtual memory
address translation and variable-sized block translation.
The 603r has a selectable 32 or 64-bit data bus and a 32-bit
address bus. The 603r interface protocol allows multiple mas-
ters to complete for system resources through a central exter-
nal arbiter. The 603r supports single-beat and burst data trans-
fers for memory accesses, and supports memory-mapped I/O.
The 603r uses an advanced, 2.5/3.3-V CMOS process techno-
logy and maintains full interface compatibility with TTL devi-
ces.
The 603r integrates in system testability and debugging fea-
tures through JTAG boundary-scan capability.
PQFP 240
DS suffix
PQFP 240
Plastic Quad Flat Pack
with heat slug under the body
and thermal drain in the board
die up
MAIN FEATURES
H
Superscalar (3 instructions per clock peak).
H
Dual 16KB caches.
H
Selectable bus clock.
H
32-bit compatibility PowerPC implementation.
H
On chip debug support.
H
P
D
typical = 2.5 Watts (200 MHz), full operating conditions.
H
P
D
max = 4 Watts (200 MHz), full operating conditions.
H
Nap, doze and sleep modes for power savings.
H
Branch folding.
H
64-bit data bus (32-bit data bus option).
H
4-Gbyte direct addressing range.
H
Pipelined single/double precision float unit.
H
H
H
H
IEEE 754 compatible FPU.
IEEE P 1149-1 test mode (JTAG/C0P).
f
int
max = 200 MHz.
f
bus
max = 75 MHz.
Compatible CMOS input / TTL Output.
SCREENING / QUALITY / PACKAGING
This product is manufactured in full compliance with:
H
H
H
H
H
PQFP 240 : According to TCS standards (planned)
Commercial temperature range (T
c
= 0°C, T
c
= +70°C)
Industrial temperature range (T
c
= –40°C, T
c
= +80°C)
Internal // I/O Power Supply = 2.5
±
5 % // 3.3 V
±
5 %.
240 pin PQFP package, die up, with heat slug and thermal
drain in the board.
November 1999
1/6
TSPC603R
1.1. Absolute maximum ratings
Absolute maximum ratings are stress rating only and functional operation at the maximum is not guaranteed. Stresses beyond those
listed may affect device reliability or cause permanent damage to the device
Table 1 : Absolute maximum rating for the 603r
Parameter
Core supply voltage
PLL supply voltage
I/O supply voltage
Input voltage
Storage temperature range
Maximum junction temperature
Notes:
Symbol
V
dd
AV
dd
OV
dd
V
in
T
stg
Tj
Min
-0.3
-0.3
-0.3
-0.3
-40
Max
2.75
2.75
3.6
5.5
+125
+ 125
Unit
V
V
V
V
°C
°C
1. Functional operating conditions are given in AC and DC electrical specifications. Stresses beyond the absolute maximums listed may affect
device reliability or cause permanent damage to the device.
2.
Caution
: Input voltage must not be greater than OVdd by more than 2.5 V at any times, including during power-on reset.
3.
Caution
: OVdd voltage must not be greater than Vdd/AVdd by more than 1.2 V at any times, including during power-on reset.
4.
Caution
: Vdd/AVdd voltage must not be greater than OVdd by more than 0.4 V at any times, including during power-on reset.
1.2. Recommanded Operating Conditions
These are the recommanded conditions. Proper device operation outside of these conditions is not guaranteed.
Parameter
Core supply voltage
PLL supply voltage
I/O supply voltage
Input voltage
Operating temperature
1.3. Thermal characteristics
Symbol
V
dd
AV
dd
OV
dd
V
in
T
c
Min
2.375
2.375
3.135
GND
–40
Max
2.625
2.625
3.465
5.5
+80
Unit
V
V
V
V
°C
The junction temperature can be calculated from the junction to ambient thermal resistance, as follow:
Junction temperature:
T
j =
T
a
+ R
ja
* P
Where:
T
a
is the ambient temperature in the vicinity of the device
R
ja
is the die junction–to–ambiant thermal resistance of the device
P is the power dissipated by the device
Assuming a T
a
of 70°C and a consumption (P) of 4 Watts, the junction temperature of the device would be as follow:
T
j =
70°C + R
ja
* 4 Watts.
Assuming an air velocity of 400 feet/mn, the associated overall thermal resistance and junction temperature is following:
T
j =
70°C + 13.3 * 4 = 123.2
°C
R
ja
(°C/W)
Air Flow (ft/min) with thermal drain in the board
0
19.4
100
16.8
200
15.1
400
13.3
600
11.2
2/6
TSPC603R
1.3.1.Power dissipation
Table 2 : Power dissipation
Vdd/AVdd = 2.5
±
5 % V dc, OVdd = 3.3
±
5 % V dc, GND = 0 V dc, 0°C
≤
T
C
≤
80°C
CPU clock Frequency
166 MHz
Full-On Mode (DPM Enabled)
Typical
Max
Doze Mode
Typical
Nap Mode
Typical
Sleep Mode
Typical
96
110
mW
100
120
mW
1.5
1.7
W
2.1
3.2
2.5
4.0
W
W
200 MHz
Units
Sleep Mode-PLL Disabled
Typical
60
60
mW
Sleep Mode-PLL and SYSCLK Disabled
Typical
Maximum
Notes:
1 These values apply for all valid PLL_CFG[0–3] settings and do not include output driver power (OVDD) or analog supply power (AVDD).
OVDD power is system dependent but is typically
≤
10% of VDD. Worst–case AVDD = 15 mW.
2 Typical power is an average value measured at VDD=AVDD=2.5 V, OVV=3.3 V, in a system executing typical applications and benchmark
sequences.
3 Maximum power is measured at VDD=2.625 V using a worst–case instruction mix.
25
60
25
60
mW
mW
3/6
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