CMOS STATIC RAM
64K (16K x 4-BIT)
Integrated Device Technology, Inc.
IDT7188S
IDT7188L
FEATURES:
• High-speed (equal access and cycle times)
— Military: 25/35/45/55/70/85ns (max.)
• Low power consumption
• Battery backup operation — 2V data retention (L version
only)
• Available in high-density industry standard 22-pin, 300
mil ceramic DIP
• Produced with advanced CMOS technology
• Inputs/outputs TTL-compatible
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT7188 is a 65,536-bit high-speed static RAM
organized as 16K x 4. It is fabricated using IDT’s high-
performance, high-reliability technology — CMOS. This state-
of-the-art technology, combined with innovative circuit design
techniques, provides a cost effective approach for memory
intensive applications.
Access times as fast as 25ns are available. The IDT7188
offers a reduced power standby mode, I
SB1
, which is activated
when
CS
goes HIGH. This capability significantly decreases
power while enhancing system reliability. The low-power
version (L) version also offers a battery backup data retention
capability where the circuit typically consumes only 30µW
operating from a 2V battery.
All inputs and outputs are TTL-compatible and operate
from a single 5V supply. The IDT7188 is packaged in 22-pin,
300 mil ceramic DIP providing excellent board-level packing
densities.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A
0
V
CC
GND
65,536-BIT
MEMORY ARRAY
DECODER
A
13
I/O
0
I/O
1
I/O
2
I/O
3
COLUMN I/O
INPUT
DATA
CONTROL
CS
WE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2989 drw 01
MILITARY TEMPERATURE RANGE
©1996
Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
AUGUST 1996
6.3
DSC-2989/7
1
IDT7188S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY TEMPERATURE RANGE
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Rating
Com’l.
Mil.
–0.5 to +7.0
Unit
V
Terminal Voltage –0.5 to +7.0
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
Power Dissipation
DC Output
Current
0 to +70
–55 to +125
–55 to +125
1.0
50
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
CS
GND
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
D22-1
17
16
15
14
13
12
V
CC
A
13
A
12
A
11
A
10
A
9
I/O
3
I/O
2
I/O
1
I/O
0
WE
2989 drw 02
T
A
T
BIAS
T
STG
P
T
I
OUT
–55 to +125
–65 to +135
–65 to +150
1.0
50
°C
°C
°C
W
mA
DIP
TOP VIEW
NOTE:
2989 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz, V
CC
= 0v))
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
6
Unit
pF
pF
PIN DESCRIPTIONS
Name
A
0
–A
13
CS
WE
Description
Address Inputs
Chip Select
Write Enable
Data Input/Output
Power
Ground
2989 tbl 01
NOTE:
2989 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
Typ.
5.0
0
—
—
Max. Unit
5.5
0
6.0
0.8
V
V
V
V
I/O
0-3
V
CC
GND
NOTE:
2989 tbl 05
1. V
IL
(min.) = –3.0V for pulse width less than 20ns,once per cycle.
TRUTH TABLE
(1)
Mode
Standby
Read
Write
CS
WE
I/O
High Z
D
OUT
D
IN
Power
Standby
Active
Active
2989 tbl 02
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Commercial
Temperature
–55°C to +125°C
0°C to +70°C
GND
0V
0V
V
CC
5V
±
10%
5V
±
10%
2989 tbl 06
H
L
L
X
H
L
NOTE:
1. H = V
IH
, L = V
IL
, X = don't care.
6.3
2
IDT7188S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
V
CC
= 5.0V
±
10%
IDT7188S
Symbol
|I
LI
|
|I
LO
|
V
OL
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Test Condition
V
CC
= Max.,
V
IN
= GND to V
CC
V
CC
= Max.,
CS
= V
IH,
V
OUT
= GND to V
CC
I
OL
= 10mA, V
CC
= Min.
I
OL
= 8mA, V
CC
= Min.
V
OH
Output High Voltage
I
OH
= –4mA, V
CC
= Min.
—
2.4
MIL.
COM’L.
MIL.
COM’L.
Min.
—
—
—
—
Max.
10
5
10
5
0.5
0.4
—
IDT7188L
Min.
—
—
—
—
—
—
2.4
Max.
5
2
5
2
0.5
0.4
—
V
2989 tbl 07
Unit
µA
µA
V
DC ELECTRICAL CHARACTERISTICS
(1)
(V
CC
= 5V
±
10%, V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
7188S25
7188L25
Symbol
I
CC1
Parameter
Operating Power
Supply Current
CS
= V
IL
, Outputs Open
V
CC
= Max., f = 0
(2)
Dynamic Operating
Current
CS
= V
IL
, Outputs Open
V
CC
= Max., f = f
MAX(2)
Standby Power Supply
Current (TTL Level)
CS
≥
V
IH
, V
CC
= Max.,
Outputs Open, f = f
MAX(2)
Full Standby Power
Supply Current (CMOS
Level)
CS
≥
V
HC
,
V
CC
=Max., V
IN
≥
V
HC
or
V
IN
≤
V
LC
, f = 0
(2)
Power
S
L
S
L
S
L
S
Com’l.
Mil.
7188S35
7188L35
Com’l.
Mil.
7188S45
7188L45
Com’l.
Mil.
7188S55/70
7188L55/70
Com’l.
Mil.
7188S85
7188L85
Com’l.
Mil.
Unit
mA
—
—
—
—
—
—
—
105
80
155
120
60
40
20
—
—
—
—
—
—
—
105
80
140
115
50
40
20
—
—
—
—
—
—
—
105
80
140
110
50
35
20
—
—
—
—
—
—
—
105
80
140
110
50
35
20
—
—
—
—
—
—
—
105
80
140
105
50
35
20
I
CC2
mA
I
SB
mA
I
SB1
mA
L
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
2989 tbl 08
NOTES:
1. All values are maximum guaranteed values.
2. At f = f
MAX
address and data inputs are cycling at the maximum frequency of read cycles of 1/t
RC
. f = 0 means no input lines change.
6.3
3
IDT7188S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY TEMPERATURE RANGE
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) V
HC
= V
CC
- 0.2V
Typ.
(1)
V
CC
@
Symbol
V
DR
I
CCDR
t
CDR(3)
t
R(3)
|I
LI
|
(3)
Max.
V
CC
@
2.0V
—
600
150
—
—
2
3.0V
—
900
225
—
—
2
Unit
V
µA
ns
ns
µA
2989 tbl 09
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
Input Leakage Current
Test Condition
—
MIL.
COM’L.
CS
Min.
2.0
—
—
0
t
RC(2)
—
2.0v
—
10
10
—
—
—
3.0V
—
15
15
—
—
—
≥
V
HC
V
IN
≥
V
HC
or
≤
V
LC
NOTES:
1. T
A
= +25°C.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed by device characterization but is not production tested.
LOW V
CC
DATA RETENTION WAVEFORM
DATA
RETENTION
MODE
4.5V
t
CDR
CS
V
IH
V
DR
≥2V
V
DR
V
IH
2989 drw 03
V
CC
4.5V
t
R
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2989 tbl 10
5V
480Ω
DATA
OUT
255Ω
30pF*
5V
480
Ω
DATA
OUT
255
Ω
5pF*
2989 drw 04
2989 drw 05
Figure 1. AC Test Load
*Includes scope and jig capacitances
Figure 2. AC Test Load
(for t
HZ
, t
LZ
, t
WZ
, t
OHZ
and t
OW
)
6.3
4
IDT7188S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, All Temperature Ranges)
7188S25
7188L25
7188S35/45
7188L35/45
7188S55/70
7188L55/70
7188S85
7188L85
Symbol
Read Cycle
t
RC
t
AA
t
ACS
t
OH
t
LZ(1)
t
HZ(1)
t
PU(1)
t
PD(1)
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change
Output Selection to Output in Low-Z
Chip Deselect to Output in High-Z
Chip Select to Power Up Time
Chip Deselect to Power Down Time
25
—
—
5
5
—
0
—
—
25
25
—
—
10
—
25
35/45
—
—
5
5
—
0
—
—
35/45
35/45
—
—
14
—
35/45
55/70
—
—
5
5
—
0
—
—
55/70
55/70
—
—
20/25
—
55/70
85
—
—
5
5
—
0
—
—
85
85
—
—
30
—
85
ns
ns
ns
ns
ns
ns
ns
ns
2989 tbl 11
NOTES:
1. This parameter is guaranteed by device characterization but is not production tested.
TIMING WAVEFORM OF READ CYCLE NO. 1
(1, 2)
t
RC (5)
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA VALID
DATA VALID
2989 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 2
(1, 3)
t
RC (5)
CS
t
ACS
t
LZ (4)
DATA
OUT
t
PU
I
CC
V
CC
SUPPLY
CURRENT I
SB
DATA VALID
t
HZ (4)
HIGH IMPEDANCE
t
PD
2989 drw 07
NOTES:
1.
WE
is HIGH for Read cycle.
2.
CS
is LOW for Read cycle.
3. Address valid prior to or coincident with
CS
transition LOW.
4. Transition is measured
±200mV
from steady state voltage.
5. All Read cycle timings are referenced from the last valid address to the first transitioning address.
6.3
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
