®
CMOS
MT9123
Dual Voice Echo Canceller
Preliminary Information
Features
•
•
•
•
•
•
•
•
•
•
•
•
Dual channel 64ms or single channel 128ms
echo cancellation
Conforms to ITU-T G.165 requirements
Narrow-band signal detection
Programmable double-talk detection threshold
Non-linear processor with adaptive suppression
threshold and comfort noise insertion
Offset nulling of all PCM channels
Controllerless mode or Controller mode with
serial interface
ST-BUS or variable-rate SSI PCM interfaces
Selectable
µ/A-Law
ITU-T G.711;
µ/A-Law
Sign
Mag; linear 2’s complement
Per channel selectable 12 dB attenuator
Transparent data transfer and mute option
19.2 MHz master clock operation
ISSUE 1
October 1996
Ordering Information
MT9123AP
28 Pin PLCC
MT9123AE
28 Pin PDIP
-40
°C
to + 85
°C
Description
The MT9123 Voice Echo Canceller implements a
cost effective solution for telephony voice-band echo
cancellation
conforming
to
ITU-T
G.165
requirements. The MT9123 architecture contains two
echo cancellers which can be configured to provide
dual channel 64 millisecond echo cancellation or
single channel 128 millisecond echo cancellation.
The MT9123 operates in two major modes:
Controller or Controllerless. Controller mode allows
access to an array of features for customizing the
MT9123 operation. Controllerless mode is for
applications where default register settings are
sufficient.
Applications
•
•
Wireless Telephony
Trunk echo cancellers
Sin
Linear/
µ/A-Law
Offset
Null
+
Non-Linear
Processor
-
Adaptive
Filter
Control
Linear/
µ/A-Law
Sout
Microprocessor
Interface
Double-Talk
Detector
Programmable
Bypass
Narrow-Band
Detector
Linear/
µ/A-Law
12dB
Attenuator
Offset
Null
Linear/
µ/A-Law
Rout
ENA2
ENB2
NLP
LAW
FORMAT
IC3
IC4
Rin
ENA1
ENB1
CONFIG1
CONFIG2
S1/DATA1
S2/DATA2
S3/CS
S4/SCLK
Echo Canceller A
Echo Canceller B
IC1
IC2
VDD
VSS
PWRDN
F0od
F0i
BCLK/C4i
MCLK
Figure 1 - Functional Block Diagram
8-45
MT9123
Preliminary Information
Figure 2 - Pin Connections
Pin Description
Pin #
1
Name
ENA1
Description
SSI Enable Strobe / ST-BUS Mode for Rin/Sout (Input).
This pin has dual functions
depending on whether SSI or ST-BUS is selected.
For SSI, this strobe must be present for frame synchronization. This is an active high channel
enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer for Echo Canceller A
on Rin/Sout pins. Strobe period is 125 microseconds.
For ST-BUS, this pin, in conjunction with the ENB1 pin, will select the proper ST-BUS mode for
Rin/Sout pins (see ST-BUS Operation description). The selected mode applies to both Echo
Canceller A and B.
2
ENB1
SSI Enable Strobe / ST-BUS Mode for Rin/Sout (Input).
This pin has dual functions
depending on whether SSI or ST-BUS is selected.
For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial
PCM data transfer for Echo Canceller B on Rin/Sout pins. Strobe period is 125 microseconds.
For ST-BUS, this pin, in conjunction with the ENA1 pin, will select the proper ST-BUS mode for
Rin/Sout pins (see ST-BUS Operation description). The selected mode applies to both Echo
Canceller A and B.
3
ENA2
SSI Enable Strobe / ST-BUS Mode for Sin/Rout (Input).
This pin has dual functions
depending on whether SSI or ST-BUS is selected.
For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial
PCM data transfer for Echo Canceller A on Sin/Rout pins. Strobe period is 125 microseconds.
For ST-BUS, this pin, in conjunction with the ENB2 pin, will select the proper ST-BUS mode for
Sin/Rout pins (see ST-BUS Operation description). The selected mode applies to both Echo
Canceller A and B.
8-46
LAW
FORMAT
PWRDN
IC3
IC4
S4/SCLK
S3/CS
ENA1
ENB1
ENA2
ENB2
Rin
Sin
VSS
MCLK
IC1
NLP
IC2
LAW
FORMAT
PWRDN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PDIP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CONFIG2
CONFIG1
BCLK/C4i
F0i
Rout
Sout
VDD
F0od
S1/DATA1
S2/DATA2
S3/CS
S4/SCLK
IC4
IC3
12
13
14
15
16
17
18
Rin
Sin
VSS
MCLK
IC1
NLP
IC2
4
3
2
1
28
27
26
•
ENB2
ENA2
ENB1
ENA1
CONFIG2
CONFIG1
BCLK/C4i
5
6
7
8
9
10
11
PLCC
25
24
23
22
21
20
19
F0i
Rout
Sout
VDD
F0od
S1/DATA1
S2/DATA2
Preliminary Information
Pin Description (continued)
Pin #
4
Name
ENB2
Description
MT9123
SSI Enable Strobe / ST-BUS Mode for Sin/Rout (Input).
This pin has dual functions
depending on whether SSI or ST-BUS is selected.
For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial
PCM data transfer for Echo Canceller B on Sin/Rout pins. Strobe period is 125 microseconds.
For ST-BUS, this pin, in conjunction with the ENA2 pin, will select the proper ST-BUS mode for
Sin/Rout pins (see ST-BUS Operation description). The selected mode applies to both Echo
Canceller A and B.
5
Rin
Receive PCM Signal Input (Input).
128 kbit/s to 4096 kbit/s serial PCM input stream. Data
may be in either companded or 2’s complement linear format. Two PCM channels are time-
multiplexed on this pin. These are the Receive Input reference channels for Echo Cancellers
A and B. Data bits are clocked in following SSI or ST-BUS timing requirements.
Send PCM Signal Input (Input).
128 kbit/s to 4096 kbit/s serial PCM input stream. Data may
be in either companded or 2’s complement linear format. Two PCM channels are time-
multiplexed on this pin. These are the Send Input channels (after echo path) for Echo
Cancellers A and B. Data bits are clocked in following SSI or ST-BUS timing requirements.
Digital Ground.
Nominally 0 volts.
Master Clock (Input).
Nominal 20 MHz Master Clock input. May be connected to an
asynchronous (relative to frame signal) clock source.
Internal Connection 1 (Input).
Must be tied to Vss.
Non-Linear Processor Control (Input).
Controllerless Mode: An active high enables the Non-Linear Processors in Echo Cancellers A
and B. Both NLP’s are disabled when low. Intended for conformance testing to G.165 and it is
usually tied to Vdd for normal operation.
Controller Mode: This pin is ignored (tie to Vdd or Vss). The non-linear processor operation is
controlled by the NLPDis bit in Control Register 2. Refer to the Register Summary.
6
Sin
7
8
9
10
VSS
MCLK
IC1
NLP
11
12
IC2
LAW
Internal Connection 2 (Input).
Must be tied to Vss.
A/µ Law Select (Input).
An active low selects
µ−Law
companded PCM. When high, selects
A-Law companded PCM. This control is for both echo cancellers and is valid for both
controller and controllerless modes.
13
FORMAT ITU-T/Sign Mag (Input).
An active low selects sign-magnitude PCM code. When high,
selects ITU-T (G.711) PCM code. This control is for both echo cancellers and is valid for both
controller and controllerless modes.
PWRDN Power-down (Input).
An active low resets the device and puts the MT9123 into a low-power
stand-by mode.
IC3
IC4
S4/S3
Internal Connection 3 (Output).
Must be left unconnected.
Internal Connection 4 (Output).
Must be left unconnected.
Selection of Echo Canceller B Functional States (Input).
Controllerless Mode: Selects Echo Canceller B functional states according to Table 2.
Controller Mode: S4 and S3 pins become SCLK and CS pins respectively.
14
15
16
17/18
17
18
SCLK
CS
Serial Port Synchronous Clock (Input).
Data clock for the serial microport interface.
Chip Select (Input).
Enables serial microport interface data transfers. Active low.
8-47
MT9123
Pin Description (continued)
Pin #
19/20
Name
S2/S1
Description
Preliminary Information
Selection of Echo Canceller A Functional States (Input).
Controllerless Mode: Selects Echo Canceller A functional states according to Table 2.
Controller Mode: S2 and S1 pins become DATA2 and DATA1 pins respectively.
19
DATA2
Serial Data Receive (Input).
In Motorola/National serial microport operation, the DATA2 pin is used for receiving data. In
Intel serial microport operation, the DATA2 pin is not used and must be tied to Vss or Vdd.
Serial Data Port (Bidirectional).
In Motorola/National serial microport operation, the DATA1 pin is used for transmitting data. In
Intel serial microport operation, the DATA1 pin is used for transmitting and receiving data.
Delayed Frame Pulse Output (Output).
In ST-BUS operation, this pin generates a delayed
frame pulse after the 4th channel time slot and is used for daisy-chaining multiple ST-BUS
devices. See Figures 5 to 8.
In SSI operation, this pin outputs logic low.
20
DATA1
21
F0od
22
23
VDD
Sout
Positive Power Supply.
Nominally 5 volts.
Send PCM Signal Output (Output).
128 kbit/s to 4096 kbit/s serial PCM output stream. Data
may be in either companded or 2’s complement linear PCM format. Two PCM channels are
time-multiplexed on this pin. These are the Send Out signals after echo cancellation and Non-
linear processing. Data bits are clocked out following SSI or ST-BUS timing requirements.
Receive PCM Signal Output (Output).
128 kbit/s to 4096 kbit/s serial PCM output stream.
Data may be in either companded or 2’s complement linear PCM format. Two PCM channels
are time-multiplexed on this pin. This output pin is provided for convenience in some
applications and may not always be required. Data bits are clocked out following SSI or ST-
BUS timing requirements.
Frame Pulse (input).
In ST-BUS operation, this is a frame alignment low going pulse. SSI
operation is enabled by connecting this pin to Vss.
24
Rout
25
26
F0i
BCLK/C4i Bit Clock/ST-BUS Clock (Input).
In SSI operation, BCLK pin is a 128 kHz to 4.096 MHz bit
clock. This clock must be synchronous with ENA1, ENA2, ENB1 and ENB2 enable strobes.
In ST-BUS operation, C4i pin must be connected to the 4.096MHz (C4) system clock.
27/28 CONFIG1/ Device Configuration Pins (Inputs).
When CONFIG1 and CONFIG2 pins are both logic 0,
CONFIG2
the MT9123 serial microport is enabled. This configuration is defined as Controller Mode.
When CONFIG1 and CONFIG2 pins are in any other logic combination, the MT9123 is
configured in Controllerless Mode. See Table 3.
Notes:
1. All unused inputs should be connected to logic low or high unless otherwise stated. All outputs should be left open circuit when not used.
2. All inputs have TTL compatible logic levels except for MCLK, Sin and Rin pins which have CMOS compatible logic levels and PWRDN
pin which has Schmitt trigger compatible logic levels.
3. All outputs are CMOS pins with CMOS logic levels.
8-48
Preliminary Information
Functional Description
The MT9123 architecture contains two individually
controlled echo cancellers (Echo Canceller A and B).
They can be set in three distinct configurations:
Normal, Back-to-Back and Extended Delay (see
Figure 3). Under Normal configuration, the two echo
cancellers are positioned in parallel providing 64
millisecond echo cancellation in two channels
simultaneously. In Back-to-Back configuration, the
two echo cancellers are positioned to cancel echo
coming from both directions in a single channel. In
Extended-Delay configuration, the two echo
cancellers are internally cascaded into one 128
millisecond echo canceller.
Each echo canceller contains the following main
elements (see Figure 1).
•
•
•
•
•
Adaptive Filter for estimating the echo channel
Subtracter for cancelling the echo
Double-Talk detector for disabling the filter
adaptation during periods of double-talk
Non-Linear Processor for suppression of
residual echo
Narrow-Band Detector for preventing Adaptive
Filter divergence caused by narrow-band
signals
•
•
•
•
MT9123
Offset Null filters for removing the DC
component in PCM channels
12dB attenuator for signal attenuation
Serial controller interface compatible with
Motorola, National and Intel microcontrollers
PCM encoder/decoder compatible with
µ/A-
Law ITU-T G.711,
µ/A-Law
Sign-Mag or linear
2’s complement coding
The MT9123 has two modes of operation:
Controllerless
and
Controller.
Controllerless mode is
intended for applications where customization is not
required. Controller mode allows access to all
registers for customizing the MT9123 operation.
Refer to Table 7 for a complete list. Controller mode
is selected when CONFIG1 and CONFIG2 pins are
both connected to Vss.
Each echo canceller in the MT9123 has four
functional states:
Mute, Bypass, Disable Adaptation
and
Enable Adaptation.
These are explained in the
section entitled Echo Canceller Functional States.
PORT 2
PORT 2
Sin
echo
path A
channel A
Rout
E.C.A
channel B
+
-
echo
path B
channel B
Rout
E.C.B
Optional -12dB pad
Optional -12dB pad
PORT 1
channel A
+
-
Sout
PORT 1
channel A
+
-
Adaptive
Filter (64ms)
Rin
Sout
Sin
echo
path A
Adaptive Filter
(128 ms)
channel A
Rin
E.C.A
Optional -12dB pad
Rout
b) Extended Delay Configuration (128ms)
PORT 2
Sin
-
echo
path
+
Optional -12dB pad
PORT 1
Sout
Adaptive
Filter (64ms)
-
+
E.C.A
Optional -12dB pad
Adaptive
Filter (64ms)
Adaptive
Filter (64ms)
echo
path
Rin
E.C.B
a) Normal Configuration (64ms)
c) Back-to-Back Configuration (64ms)
Figure 3 - Device Configuration
8-49
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