ISO-CMOS ST-BUS
TM
Family
MT8952B
HDLC Protocol Controller
Data Sheet
Features
•
•
•
•
•
•
•
•
Formats data as per X.25 (CCITT) level-2
standards
Go-Ahead sequence generation and detection
Single byte address recognition
Microprocessor port and directly accessible
registers for flexible operation and control
19 byte FIFO in both send and receive paths
Handshake signals for multiplexing data links
High speed serially clocked output (2.5 Mbps)
ST-BUS compatibility with programmable channel
selection for data and separate timeslot for
control information
Independent watchdog timer
Facility to disable protocol functions
Low power ISO-CMOS technology
•
•
•
•
Ordering Information
MT8952BE1
MT8952BP1
MT8952BPR1
MT8952BS1
28
28
28
28
Pin
Pin
Pin
Pin
PDIP*
PLCC*
PLCC*
SOIC*
August 2011
Tubes
Tubes
Tape & Reel
Tubes
*Pb Free Matte Tin
-40C to +85C
Digital sets, PBXs and private packet networks
D-channel controller for ISDN basic access
C-channel controller to Digital Network Interface
Circuits (typically MT8972)
Interprocessor communication
•
•
•
Description
The MT8952B HDLC Protocol Controller frames and
formats data packets according to X.25 (Level 2)
Recommendations from the CCITT.
Applications
•
Data link controllers and protocol generators
TEOP
C-Channel
Interface
Transmit
FIFO
Transmit
Logic
Zero
Insertion
Flag/Abort
Generator
CDSTo
D0-D7
Micro
Processor
R/W
CS
E
IRQ
WD
Interface
Control
Address
Decoder
Interrupt
Registers
and Status
Register
Timing
Logic
F0i
CKi
RxCEN
TxCEN
A0-A3
V
DD
V
SS
RST
Receive
FIFO
Receive Logic
Address
Detection
Zero
Deletion
Flag/Abort/
Idle
Detection
CDSTi
REOP
Figure 1 - Functional Block Diagram
1
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Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved.
MT8952B
Data Sheet
TxCEN
RxCEN
CDSTo
CDSTi
WD
IRQ
A0
A1
A2
A3
CS
E
R/W
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
RST
F0i
CKi
TEOP
REOP
D7
D6
D5
D4
D3
D2
D1
D0
4
3
2
1
28
27
26
CDSTi
CDSTo
RxCEN
TxCEN
VDD
RST
F0i
28 PIN PDIP/SOIC
Figure 2 - Pin Connections
Change Summary
Changes are from the November 2005 issue to the August 2011 issue.
Page
1
Pin Description
Pin No.
1
Name
TxCEN
Item
Ordering Information
Change Summary
Removed leaded packages as per PCN notice.
Description
Transmit Clock Enable -
This active LOW input enables the transmit section in the External
Timing Mode. When LOW, CDSTo is enabled and when HIGH, CDSTo is in high impedance
state. If the Protocol Controller is in the Internal Timing Mode, this input is ignored.
Receive Clock Enable -
This active LOW input enables the receive section in the External
Timing Mode. When LOW, CDSTi is enabled and when HIGH, the clock to the receive
section is inhibited. If the Protocol Controller is in the Internal Timing Mode, this input is
ignored.
C and D channel Output in ST-BUS format
- This is the serial formatted data output from
the transmitter in NRZ form. It is in ST-BUS format if the Protocol Controller is in Internal
Timing Mode with the data in selected timeslots (0,2,3 and 4) and the C-channel information
in timeslot No. 1. If the Protocol Controller is in External Timing Mode, the formatted data is
output on the rising edge of the clock (CKi) when TxCEN LOW. If TxCEN is HIGH, CDSTo is
in high impedance state.
2
RxCEN
3
CDSTo
2
Zarlink Semiconductor Inc.
E
R/W
VSS
D0
D1
D2
D3
12
13
14
15
16
17
18
WD
IRQ
A0
A1
A2
A3
CS
5
6
7
8
9
10
11
25
24
23
22
21
20
19
CKi
TEOP
REOP
D7
D6
D5
D4
28 PIN PLCC
MT8952B
Pin Description (continued)
Pin No.
4
Name
CDSTi
Description
Data Sheet
C and D channel Input in ST-BUS format -
This is the serial formatted data input to the
receiver in NRZ form. It must be in ST-BUS format if the Protocol Controller is in Internal
Timing Mode with the input data in selected timeslots (0,2,3 and 4) and the C-channel
information in timeslot No.1. If the Controller is in External Timing Mode, the serial input data
is sampled on the falling edge of the clock CKi when RxCEN is LOW. If RxCEN is HIGH, the
clock to receive section is inhibited.
Watch-Dog Timer output
- Normally a HIGH level output, going LOW if the Watchdog timer
times out or if the external reset (RST) is held LOW. The WD output remains LOW as long
as RST is held LOW.
Interrupt Request Output (Open Drain) -
This active LOW output notifies the controlling
microprocessor of an interrupt request. It goes LOW only when the bits in the Interrupt
Enable Register are programmed to acknowledge the source of the interrupt as defined in
the Interrupt Flag Register.
Address Bus Inputs
- These bits address the various registers in the Protocol Controller.
They select the internal registers in conjunction with CS, R/W inputs and E Clock. (Refer to
Table 1.)
Chip Select Input
- This is an active LOW input enabling the Read or Write operation to
various registers in the Protocol Controller.
Enable Clock Input
- This input activates the Address Bus and R/W input and enables data
transfers on the Data Bus.
Read/Write Control -
This input controls the direction of data flow on the data bus. When
HIGH, the I/O buffer acts as an output driver and as an input buffer when LOW.
Ground (0 Volt).
Bidirectional Data Bus -
These Data Bus I/O ports allow the data transfer between the
HDLC Protocol Controller and the microprocessor.
Receive End Of Packet (Output) -
This is a HIGH going pulse that occurs for one bit
duration when a closing flag is detected on the incoming packets, or the incoming packet is
aborted, or when an invalid packet of 24 or more bits is received.
Transmit End Of Packet (Output) -
This is a HIGH going pulse that occurs for one bit
duration when a packet is transmitted correctly or aborted.
Clock Input (Bit rate clock or 2 x bit rate clock in ST-BUS format while in the Internal
Timing Mode and bit rate Clock in the External Timing Mode)
- This is the clock input
used for shifting in/out the formatted packets. It can be at bit rate (C2i) or twice the bit rate
(C4i) in ST-BUS format while the Protocol Controller is in the Internal Timing Mode. Whether
the clock should be C2i (typically 2.048 MHz) or C4i (typically 4.096 MHz) is decided by the
BRCK bit in the Timing Control Register. If the Protocol Controller is in the External Timing
Mode, it is at the bit rate.
Frame Pulse Input -
This is the frame pulse input in ST-BUS format to establish the
beginning of the frame in the Internal Timing Mode. This is also the signal clocking the
watchdog timer.
RESET Input -
This is an active LOW Schmitt Trigger input, resetting all the registers
including the transmit and receive FIFOs and the watchdog timer.
Supply (5 Volts).
5
WD
6
IRQ
7-10
A0-A3
11
12
13
14
15-22
23
CS
E
R/W
V
SS
D0-D7
REOP
24
25
TEOP
CKi
26
F0i
27
28
RST
V
DD
3
Zarlink Semiconductor Inc.
MT8952B
Address Bits
A3
0
0
0
0
0
0
0
0
1
1
A2
0
0
0
0
1
1
1
1
0
0
A1
0
0
1
1
0
0
1
1
0
0
A0
0
1
0
1
0
1
0
1
0
1
Read
FIFO Status
Receive Data
Control
Receive Address
C-Channel Control (Transmit)
Timing Control
Interrupt Flag
Interrupt Enable
General Status
C-Channel Status (Receive)
Table 1 - Register Addresses
Registers
Write
-
Data Sheet
Transmit Data
Control
Receive Address
C-Channel Control (Transmit)
Timing Control
Watchdog Timer
Interrupt Enable
-
-
Introduction
The MT8952B HDLC Protocol Controller handles bit oriented protocol structure and formats the data as per the
packet switching protocol defined in the X.25 (Level 2) recommendations of the CCITT. It transmits and receives the
packeted data (information or control) serially in a format shown in Figure 3, while providing the data transparency
by zero insertion and deletion. It generates and detects the flags, various link channel states and the abort
sequence. Further, it provides a cyclic redundancy check on the data packets using the CCITT defined polynomial.
In addition, it can generate and detect a Go Ahead sequence and recognize a single byte address in the received
frame. There is also a provision to disable the protocol functions and provide transparent access to the serial bus
through the parallel port.
Frame Format
All frames start with an opening flag and end with a closing flag as shown in Figure 3. Between these two flags, a
frame contains the data and the frame check sequence (FCS).
FLAG
One
Byte
DATA FIELD
n Bytes
(n 2)
FCS
Two
Bytes
FLAG
One
Byte
Figure 3 - Frame Format
Flag
The flag is a unique pattern of 8 bits (01111110) defining the frame boundary. The transmit section generates the
flags and appends them automatically to the frame to be transmitted. The receive section searches the incoming
packets for flags on a bit-by-bit basis and establishes frame synchronization. The flags are used only to identify and
synchronize the received frame and are not transferred to the FIFO.
4
Zarlink Semiconductor Inc.
MT8952B
Data
Data Sheet
The data field refers to the Address, Control and Information fields defined in the CCITT recommendations. A valid
frame should have a data field of at least 16 bits. The first byte in the data field is the address of the frame. If RxAD
bit in the Control Register is HIGH, the incoming packet is recognized only if the address byte matches the byte
stored in the Receive Address Register or the address byte is the All-Call Address (all ONEs). The LSB of the
Receive Address Register is set LOW permanently and the comparison is done only on upper seven bits of the
received address byte. The address detection can be limited only to the upper six bits by setting HIGH both RA6/7
and RxAD bits in the Control Register.
Frame Check Sequence (FCS)
The 16 bits following the data field are the frame check sequence bits. The generator polynomial is:
G(x)=x
16
+x
12
+x
5
+1
The transmitter calculates the FCS on all bits of the data field and transmits after the data field and before the end
flag. The receiver performs a similar computation on all bits of the received data and FCS fields and the result is
compared with FOB8
Hex
. If it matches, the received data is assumed error free. The error status of the received
packet is indicated by D7 and D6 bits in the FIFO Status Register.
Zero Insertion and Deletion
The Protocol Controller, while sending either data from the FIFO or the 16 bits FCS, checks the transmission on a
bit-by-bit basis and inserts a ZERO after every sequence of five contiguous ONEs (including the last five bits of
FCS) to ensure that the flag sequence is not simulated. Similarly the receiver examines the incoming frame content
and discards any ZERO directly following the five contiguous ONEs.
Abort
The transmitter aborts a frame by sending eight consecutive ONEs. The FA bit in the Control Register along with a
write operation to the Transmit Data Register enables the transmission of abort sequence instead of the byte
written to the register. On the receive side, the ABRT bit in the General Status Register is set whenever an abort
sequence (7 or more continuous 1’s) is received. The abort sequence causes the receiver to abandon whatever it
was doing and start searching for a start flag. The FA bit in the Interrupt Status Register is set when an abort
sequence is received following a start flag and at least four data bytes (minimum for a valid frame).
Interframe Time Fill and Link Channel States
When the HDLC Protocol Controller is not sending packets, the transmitter can be in any of three states mentioned
below depending on the status of the IFTF0 and IFTF1 bits in the Control Register. These bits are also used to
disable the protocol function to provide the transparent parallel access to the serial bus through the microprocessor
port.
Idle State
The Idle state is defined as 15 or more contiguous ONEs. When the HDLC Protocol Controller is observing this
condition on the receiving channel, the Idle bit in the General Status Register is set HIGH. On the transmit side, the
Protocol Controller ends the Idle state when data is loaded into the transmit FIFO.
Interframe Time Fill State
The Protocol Controller transmits continuous flags (7E
Hex
) in Interframe time fill state and ends this state when data
is loaded into the transmit FIFO.
5
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