ISO
2
-CMOS ST-BUS
TM
Family
MT9173/74
Digital Subscriber Interface Circuit with RxSB
Digital Network Interface Circuit with RxSB
Data Sheet
Features
•
•
•
•
•
•
•
•
•
•
Receive sync output pulse
Full duplex transmission over a single twisted pair
Selectable 80 or 160 kbit/s line rate
Adaptive echo cancellation
Up to 3 km (9173) and 4 km (9174) loop reach
ISDN compatible (2B+D) data format
Transparent modem capability
Frame synchronization and clock extraction
Zarlink ST-BUS compatible
Low power (typically 50 mW), single 5 V supply
MT9173AE
MT9173AN
MT9173AP
MT9173AE1
MT9173AP1
MT9173AN1
MT9174AE
MT9174AN
MT9174AP
December 2005
Ordering Information
24 Pin PDIP
24 Pin SSOP
28 Pin PLCC
24 Pin PDIP*
28 Pin PLCC*
24 Pin SSOP*
24 Pin PDIP
24 Pin SSOP
28 Pin PLCC
*Pb Free Matte Tin
Tubes
Tubes
Tubes
Tubes
Tubes
Tape & Reel
Tubes
Tubes
Tubes
-40°C to +85°C
Description
The MT9173 (DSIC) and MT9174 (DNIC) are
functionally identical to the MT9171/72 except for the
addition of one feature. The MT9173/74 include a
digital output pin indicating the temporal position of the
received "SYNC" bit of the biphase transmission. This
feature is especially useful for systems such as PCS
wireless base station applications requiring close
synchronization between microcells.
The MT9173 and MT9174 are identical except for the
MT9173 having a shorter loop reach. The generic
"DNIC" will be used to reference both devices unless
otherwise noted. The MT9173/74 are fabricated in
Zarlink’s ISO
2
-CMOS process.
Applications
•
•
•
•
•
T
DD
Digital PCS (DECT, CT2, PHS) base stations
requiring cell synchronization
Digital subscriber lines
High speed data transmission over twisted wires
Digital PABX line cards and telephone sets
80 or 160 kbit/s single chip modem
DSTi/Di
CDSTi/
CDi
Transmit
Interface
Prescrambler
Scrambler
Differentially
Encoded Biphase
Transmitter
Transmit
Filter &
Line Driver
L
OUT
F0/CLD
C4/TCK
MS0
MS1
MS2
RegC
Control
Register
Transmit
Timing
Master Clock
Phase Locked
Transmit/
Clock
Receive
Timing &
Control
Sync Detect
Status
Receive
Address
Echo Canceller
Error
Signal
Echo Estimate
—
DPLL
V
Bias
MUX
L
OUT
DIS
Precan
∑
+
Receive
Filter
-1
+2
L
IN
OSC2
DSTo/Do
CDSTo/
CDo
RxSB
Receive
Interface
De-
Prescrambler
Descrambler
Differentially
Encoded Biphase
Receiver
OSC1
V
DD
V
SS
V
Bias
V
Ref
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1999-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT9173/74
VRef
VBias
LOUT
NC
VDD
LIN
TEST
Data Sheet
24 PIN PDIP/ SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
Name
24
1
2
3
4,5,
6
7
8
28
2
3
4
5,7,
8
9
10
L
OUT
V
Bias
V
Ref
Line Out.
Transmit Signal output (Analog). Referenced to V
Bias
.
Internal Bias Voltage
output. Connect via 0.33
µF
decoupling capacitor to V
DD
.
Internal Reference Voltage
output. Connect via 0.33
µF
decoupling capacitor to V
DD
.
Description
MS2-MS0
Mode Select
inputs (Digital). The logic levels present on these pins select the various
operating modes for a particular application. See Table 1 for the operating modes.
RegC
RxSB
Regulator Control
output (Digital). A 512 kHz clock used for switch mode power
supplies. Unused in MAS/MOD mode and should be left open circuit.
Receive Sync Bit
output (Digital). In DN mode, this output is held high until receive
synchronization occurs (i.e., until the sync bit in Status Register =1). Once low,
indicating synchronized transmission, a high going pulse (6.24
µs
wide pulse @
160 kb/s and 12.5
µs
wide @ 80 kb/s) indicates the temporal position of the receive
"SYNC" bit in the biphase line transmission. Inactive and low in MOD mode.
Frame Pulse/C-Channel Load
(Digital). In DN mode a 244 ns wide negative pulse
input for the MASTER indicating the start of the active channel times of the device.
Output for the SLAVE indicating the start of the active channel times of the device.
Output in MOD mode providing a pulse indicating the start of the C-channel.
Control/Data ST-BUS In/Control/Data In
(Digital). A 2.048 Mbit/s serial control &
signalling input in DN mode. In MOD mode this is a continuous bit stream at the bit
rate selected.
Control/Data ST-BUS Out/Control/Data Out
(Digital). A 2.048 Mbit/s serial control &
signalling output in DN mode. In MOD mode this is a continuous bit stream at the bit
rate selected.
Negative Power Supply
(0 V).
9
11
F0/CLD
10
12
CDSTi/
CDi
CDSTo/
CDo
V
SS
11
13
12
13
14
15
DSTo/Do
Data ST-BUS Out/Data Out
(Digital). A 2.048 Mbit/s serial PCM/data output in DN
mode. In MOD mode this is a continuous bit stream at the bit rate selected.
2
Zarlink Semiconductor Inc.
CDSTi/CDi
CDSTo/CDo
VSS
DSTo/Do
DSTi/Di
F0o/RCK
NC
LOUT
VBias
VRef
MS2
MS1
MS0
RegC
RxSB
F0/CLD
CDSTi/CDi
CDSTo/CDo
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
LIN
TEST
LOUT DIS
Precan
OSC1
NC
OSC2
C4/TCK
F0o/RCK
DSTi/Di
DSTo/Do
4
3
2
1
28
27
26
²
12
13
14
15
16
17
18
MS2
NC
MS1
MS0
RegC
RxSB
F0/CLD
5
6
7
8
9
10
11
25
24
23
22
21
20
19
NC
LOUT DIS
Precan
OSC1
OSC2
NC
C4/TCK
28 PIN PLCC
MT9173/74
Pin Description (continued)
Pin #
Name
24
14
15
28
16
17
DSTi/Di
Description
Data Sheet
Data ST-BUS In/Data In
(Digital). A 2.048 Mbit/s serial PCM/data input in DN mode.
In MOD mode this is a continuous bit stream at the bit rate selected.
F0o/RCK
Frame Pulse Out/Receive Bit Rate Clock
output (Digital). In DN mode a 244 ns
wide negative pulse indicating the end of the active channel times of the device to
allow daisy chaining. In MOD mode provides the receive bit rate clock to the system.
C4/TCK
Data Clock/Transmit Baud Rate Clock
(Digital). A 4.096 MHz TTL compatible clock
input for the MASTER and output for the SLAVE in DN mode. For MOD mode this pin
provides the transmit bit rate clock to the system.
Oscillator Output.
CMOS Output.
Oscillator Input.
CMOS Input. D.C. couple signals to this pin. Refer to D.C. Electrical
Characteristics for OSC1 input requirements.
Precanceller Disable.
When held to Logic ’1’
,
the internal path from L
OUT
to the
precanceller is forced to V
Bias
thus bypassing the precanceller section. When logic ’0’,
the L
OUT
to the precanceller path is enabled and functions normally. An internal
pulldown (50 kΩ) is provided on this pin.
No Connection.
Leave open circuit
16
19
17
19
20
21
22
23
OSC2
OSC1
Precan
18
1,6,
18,
20,
25
24
26
27
28
NC
21
22
23
24
L
OUT
DIS
L
OUT
Disable.
When held to logic “1”, L
OUT
is disabled (i.e., output = V
Bias
). When
logic “0”, L
OUT
functions normally. An internal pulldown (50 kΩ) is provided on this pin.
TEST
L
IN
V
DD
Test Pin.
Connect to V
SS
.
Receive Signal
input (Analog).
Positive Power Supply
(+5 V) input.
F0
C4
DSTi
B1
7
B1
6
B1
5
B1
4
B1
3
B1
2
B1
1
B1
0
B1
7
DSTo
B1
7
B1
6
B1
5
B1
4
B1
3
B1
2
B1
1
B1
0
B1
7
F0o
Channel Time 0
Figure 3 - DV Port - 80 kbit/s (Modes 2, 3, 6)
3
Zarlink Semiconductor Inc.
MT9173/74
Data Sheet
F0
C4
DSTi
B1
7
B1
6
B1
5
B1
4
B1
3
B1
2
B1
1
B1
0
B2
7
B2
6
B2
5
B2
4
B2
3
B2
2
B2
1
B2
0
B1
7
DSTo
B1
7
B1
6
B1
5
B1
4
B1
3
B1
2
B1
1
B1
0
B2
7
B2
6
B2
5
B2
4
B2
3
B2
2
B2
1
B2
0
B1
7
F0o
Channel Time 0
Channel Time 16
Figure 4 - DV Port - 160 kbit/s (Modes 2, 3, 6)
Functional Description
The MT9173 and MT9174 are multifunction devices capable of providing high speed, full duplex digital transmission
at up to 160 kbit/s over a twisted wire pair. They use adaptive echo-cancelling techniques and transfer data in a
format compatible to the ISDN basic rate. Several modes of operation allow an easy interface to digital
telecommunication networks including PCS wireless base stations, smart telephone sets, workstations, data
terminals and computers. The device supports the 2B+D channel format (two 64 kbit/s B-channels and one
16 kbit/s D-channel) over two wires as recommended by the CCITT. The line data is converted to and from the ST-
BUS format on the system side of the network to allow for easy interfacing with other components such as the S-
interface device in an NT1 arrangement, or to digital PABX components.
Smart telephone sets with data and voice capability can be easily implemented using the MT9173/74 as a line
interface. The device’s high bandwidth and long loop length capability allows its use in a wide variety of sets. This
can be extended to provide full data and voice capability to the private subscriber by the installation of equipment in
both the home and central office or remote concentration equipment. Within the subscriber equipment the
MT9173/74 would terminate the line and encode/ decode the data and voice for transmission while additional
electronics could provide interfaces for a standard telephone set and any number of data ports supporting standard
data rates for such things as computer communications and telemetry for remote meter reading. Digital
workstations with a high degree of networking capability can be designed using the DNIC for the line interface,
offering up to 160 kbit/s data transmission over existing telephone lines. The MT9173/74 could also be valuable
within existing computer networks for connecting a large number of terminals to a computer or for intercomputer
links. With the DNIC, this can be accomplished at up to 160 kbit/s at a very low cost per line for terminal to
computer links and in many cases this bandwidth would be sufficient for computer to computer links.
Figure 1 shows the block diagram of the MT9173/74. The DNIC provides a bidirectional interface between the DV
(data/voice) port and a full duplex line operating at 80 or 160 kbit/s over a single pair of twisted wires. The DNIC has
three serial ports. The DV port (DSTi/Di, DSTo/Do), the CD (control/data) port (CDSTi/CDi, CDSTo/CDo) and a line
port (L
IN
, L
OUT
). The data on the line is made up of information from the DV and CD ports. The DNIC must combine
information received from both the DV and CD ports and put it onto the line. At the same time, the data received
from the line must be split into the various channels and directed to the proper ports. The usable data rates are 72
4
Zarlink Semiconductor Inc.
MT9173/74
Data Sheet
and 144 kbit/s as required for the basic rate interface in ISDN. Full duplex transmission is made possible through
on board adaptive echo cancellation.
The DNIC has various modes of operation which are selected through the mode select pins MS0-2. The two major
modes of operation are the MODEM (MOD) and DIGITAL NETWORK (DN) modes. MOD mode is a transparent 80
or 160 kbit/s modem. In DN mode the line carries the B and D channels formatted for the ISDN at either 80 or
160 kbit/s. In the DN mode the DV and CD ports are standard ST-BUS and in MOD mode they are transparent
serial data streams at 80 or 160 kbit/s. Other modes include: MASTER (MAS) or SLAVE (SLV) mode, where the
timebase and frame synchronization are provided externally or are extracted from the line and DUAL or SINGLE
(SINGL) port modes, where both the DV and CD ports are active or where the CD port is inactive and all
information is passed through the DV port. For a detailed description of the modes see “Operating Modes” section.
In DIGITAL NETWORK (DN) mode there are three channels transferred by the DV and CD ports. They are the B, C
and D channels. The B1 and B2 channels each have a bandwidth of 64 kbit/s and are used for carrying PCM
encoded voice or data. These channels are always transmitted and received through the DV port (Figures 3, 4, 5,
6). The C-channel, having a bandwidth of 64 kbit/s, provides a means for the system to control the DNIC and for the
DNIC to pass status information back to the system. The C-channel has a Housekeeping (HK) bit which is the only
bit of the C-channel transmitted and received on the line. The 2B+D channel bits and the HK bit are double-
buffered. The D-channel can be transmitted or received on the line with either an 8, 16 or 64 kbit/s bandwidth
depending on the DNIC’s mode of operation. Both the HK bit and the D-channel can be used for end-to-end
signalling or low speed data transfer. In DUAL port mode the C and D channels are accessed via the CD port
(Figure 7) while in SINGL port mode they are transferred through the DV port (Figures 5, 6) along with the B1 and
B2 channels.
F0
C4
DSTo
DSTi
F0o
11.7
µsec
Channel Time 0
D-Channel
Channel Time 1
C-Channel
Channel Time 2
B1-Channel
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
D
0
D
0
Figure 5 - DV Port - 80 kbit/s (Modes 0,4)
F0
C4
DSTo
DSTi
F0o
15.6
µsec
Channel Time 0
D-Channel
Channel Time 1
C-Channel
Channel Time 2
B1-Channel
Channel Time 3
B2-Channel
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
D
0
D
0
Figure 6 - DV Port - 160 kbit/s (Modes 0,4)
5
Zarlink Semiconductor Inc.
微控制器 MCU
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